The customized Aurora 8B/10B core is delivered as a set of HDL source modules in the language selected. These files are arranged in a predetermined directory structure under the project directory name provided to the IP catalog when the project is created.
If the VHDL language is selected for UltraScale devices, the IP top-level wrapper file is VHDL and the underlying design source files are Verilog.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 7].