Example Design XDC - 11.1 English

The generated Verilog example design is configured with a two-byte lane width, 3.125 Gb/s line rate, and a 125.0 MHz reference clock. The XDC file generated for the XC7VX690T-FFG1761-2 device follows:

 

################################################################################

## XDC generated for xc7vx690t-ffg1761-2 device

# 125.0MHz GT Reference clock constraint

create_clock -name GT_REFCLK1 -period 8.0    [get_ports GTHQ1_P]

####################### GT reference clock LOC #######################

set_property LOC AW9 [get_ports GTHQ1_N]

set_property LOC AW10 [get_ports GTHQ1_P]

 

# USER_CLK Constraint: Value is selected based on the line rate (3.125 Gb/s) and lane width (2-Byte)

# create_clock -name user_clk_i -period 6.400    [get_pins aurora_module_i/clock_module_i/user_clk_buf_
i/I]

 

# 20.0 ns period Board Clock Constraint

create_clock -name init_clk_i -period 20.0 [get_ports INIT_CLK_P]

 

# 20.000    ns period DRP Clock Constraint

create_clock -name drp_clk_i -period 20.000    [get_ports DRP_CLK_IN]

 

###### CDC in RESET_LOGIC from INIT_CLK to USER_CLK ##############

set_false_path -through [get_pins -hier *cdc_to*]

 

##################### Location constraint #########################

##Note: User should add LOC based upon the board

#       Below LOCs are place holders and need to be changed as per the device and board

#set_property LOC D17 [get_ports INIT_CLK_P]

#set_property LOC D18 [get_ports INIT_CLK_N]

#set_property LOC G19 [get_ports RESET]

#set_property LOC K18 [get_ports GT_RESET_IN]

#set_property LOC A20 [get_ports CHANNEL_UP]

#set_property LOC A17 [get_ports LANE_UP]

#set_property LOC Y15 [get_ports HARD_ERR]

#set_property LOC AH10 [get_ports SOFT_ERR]

#set_property LOC AD16 [get_ports ERR_COUNT[0]]

#set_property LOC Y19 [get_ports ERR_COUNT[1]]

#set_property LOC Y18 [get_ports ERR_COUNT[2]]

#set_property LOC AA18 [get_ports ERR_COUNT[3]]

#set_property LOC AB18 [get_ports ERR_COUNT[4]]

#set_property LOC AB19 [get_ports ERR_COUNT[5]]

#set_property LOC AC19 [get_ports ERR_COUNT[6]]

#set_property LOC AB17 [get_ports ERR_COUNT[7]]

#set_property LOC AC17 [get_ports FRAME_ERR]

 

 

#set_property LOC AG29 [get_ports DRP_CLK_IN]

#// DRP CLK needs a clock LOC

 

##Note: User should add IOSTANDARD based upon the board

#       Below IOSTANDARDs are place holders and need to be changed as per the device and board

#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports INIT_CLK_P]

#set_property IOSTANDARD DIFF_HSTL_II_18 [get_ports INIT_CLK_N]

#set_property IOSTANDARD LVCMOS18 [get_ports RESET]

#set_property IOSTANDARD LVCMOS18 [get_ports GT_RESET_IN]

 

#set_property IOSTANDARD LVCMOS18 [get_ports CHANNEL_UP]

#set_property IOSTANDARD LVCMOS18 [get_ports LANE_UP]

#set_property IOSTANDARD LVCMOS18 [get_ports HARD_ERR]

#set_property IOSTANDARD LVCMOS18 [get_ports SOFT_ERR]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[0]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[1]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[2]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[3]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[4]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[5]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[6]]

#set_property IOSTANDARD LVCMOS18 [get_ports ERR_COUNT[7]]

#set_property IOSTANDARD LVCMOS18 [get_ports FRAME_ERR]

 

 

#set_property IOSTANDARD LVCMOS18 [get_ports DRP_CLK_IN]

#// DRP CLK needs a clock IOSTDLOC

 

##################################################################

 

 

############################### GT LOC ###################################

set_property LOC GTHE2_CHANNEL_X1Y4 [get_cells aurora_module_i/aurora_8b10b_0_i/inst/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/
gthe2_i]

The preceding XDC is provided for reference. The example design XDC is created automatically when the core is generated from the Vivado design tools.