This section contains information about simulating IP in the Vivado design suite. For comprehensive information about Vivado design suite simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 9].
IMPORTANT: For cores targeting UltraScale, 7 series or Zynq 7000 devices, UNIFAST libraries are not supported. AMD IP is tested and qualified with UNISIM libraries only.
The Aurora 8B/10B core delivers a demonstration test bench for the example design. The TEST COMPLETED SUCCESSFULLY message signifies the completion of the example design simulation.
Note: The Reached max. simulation time limit message means that simulation was not successful. See Debugging for more information.
Simulating the duplex core is a single-step process after generating an example design. Simplex core simulation requires partner generation. The partner core is generated automatically and the synthesized netlist is available under the simulation file set when clicking Open IP Example Design. Due to the synthesizing of the partner core, opening a simplex core example design takes more time than the duplex example design generation.
Note: Simulation requires that the Labtools option to be unchecked.