Table: User I/O Ports (TX) and Table: User I/O Ports (RX) list duplex and simplex core AXI4-Stream TX and RX data port descriptions.
Name |
Direction |
Clock Domain |
Description |
---|---|---|---|
USER_DATA_S_AXI_TX |
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s_axi_tx_tdata[0:(8n–1)] or s_axi_tx_tdata[(8n–1):0] |
Input |
user_clk |
Outgoing data. n is the number of bytes computed as Number of lanes x Lane Width. |
s_axi_tx_tready |
Output |
user_clk |
Asserted when signals from the source are accepted and when outgoing data is ready to send. |
s_axi_tx_tlast(1) |
Input |
user_clk |
Signals the end of the frame. |
s_axi_tx_tkeep[0:(n–1)] or s_axi_tx_tkeep[(n–1):0](1) |
Input |
user_clk |
Specifies the number of valid bytes in the last data beat; valid only while s_axi_tx_tlast is asserted. s_axi_tx_tkeep is the byte qualifier that indicates whether the content of the associated byte of s_axi_tx_tdata is valid or not. The Aurora 8B/10B core expects the data to be filled continuously from LSB to MSB. There cannot be invalid bytes interleaved with the valid s_axi_tx_tdata bus. |
s_axi_tx_tvalid |
Input |
user_clk |
Asserted when outgoing AXI4-Stream signals or signals from the source are valid. |
Notes: 1.This port is not available if the Streaming interface option is chosen. |
Name |
Direction |
Clock Domain |
Description |
---|---|---|---|
USER_DATA_M_AXI_RX |
|||
m_axi_rx_tdata[0:8(n–1)] or m_axi_rx_tdata[8(n–1):0] |
Output |
user_clk |
Incoming data from channel partner (Ascending bit order). |
m_axi_rx_tlast(1) |
Output |
user_clk |
Signals the end of the incoming frame (asserted for a single user clock cycle). |
m_axi_rx_tkeep[0:(n–1)] or m_axi_rx_tkeep[(n–1):0](1) |
Output |
user_clk |
Specifies the number of valid bytes in the last data beat. |
m_axi_rx_tvalid |
Output |
user_clk |
Asserted when outgoing data and control signals or data and control signals from an Aurora 8B/10B core are valid. |
Notes: 1.This port is not available if the Streaming interface option is chosen. |