Features - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID

PG046

Release Date

2023-10-19

Version

11.1 English

•General-purpose data channels with throughput range from 480 Mbps to 84.48 Gbps

•Supports up to 16 consecutively bonded 7 series GTX/GTH, UltraScale™ GTH or UltraScale+ GTH transceivers and up to four bonded GTP transceivers

•Aurora 8B/10B protocol specification v2.3 compliant

•Low resource cost (see Resource Utilization)

•Easy-to-use AXI4-Stream based framing (or streaming) and flow control interfaces

•Automatically initializes and maintains the channel

•Full-duplex or simplex operation

•16-bit additive scrambler/descrambler

•16-bit or 32-bit Cyclic Redundancy Check (CRC) for user data

•Hot-plug logic

•Configurable DRP/INIT clock

•Single/Differential clocking option for GTREFCLK and core INIT_CLK

LogiCORE IP Facts Table
Core Specifics
Supported Device Family⁽¹⁾	AMD UltraScale+™⁽²⁾, AMD UltraScale™⁽²⁾, AMD Zynq™ 7000, AMD 7 Series⁽³⁾
Supported User Interfaces	AXI4-Stream
Resources	Performance and Resource Utilization web page
Provided with Core
Design Files	Register transfer level (RTL)
Example Design	Verilog and VHDL⁽²⁾
Test Bench	Verilog and VHDL⁽⁴⁾
Constraints File	Xilinx Design Constraints (XDC)
Simulation Model	Source HDL with SecureIP transceiver simulation models
Supported S/W Driver	N/A
Tested Design Flows⁽⁵⁾
Design Entry	AMD Vivado™ Design Suite
Simulation	For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing.
Synthesis	Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 54367
All Vivado IP Change Logs	Master Vivado IP Change Logs: 72775
Support web page
Notes: 1.For a complete list of supported devices and configurations, see the Vivado IP catalog and associated FPGA data sheets. 2.For more information, see the Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 20], Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 19], Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref 21], and Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 22]. 3.For more information, see the 7 Series FPGAs Overview (DS180) [Ref 17] and the UltraScale Architecture and Product Overview (DS890) [Ref 18]. 4.The IP core is delivered as Verilog source code and comes with an example design and supporting modules for simple simulation and hardware demonstration. 5.For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing.