The RX submodules have no built-in elastic buffer for user data. As a result, there is no m_axi_rx_tready signal on the RX AXI4-Stream interface. The only way for the user application to control the flow of data from an Aurora 8B/10B channel is to use one of the core optional flow control features.
The m_axi_rx_tvalid signal is asserted concurrently with the first word of each frame from the Aurora 8B/10B core. m_axi_rx_tlast is asserted concurrently with the last word or partial word of each frame. The m_axi_rx_tkeep port indicates the number of valid bytes in the final word of each frame.The m_axi_rx_tkeep signal is only valid when m_axi_rx_tlast is asserted.
The Aurora 8B/10B core can deassert m_axi_rx_tvalid anytime, even during a frame. The core can occasionally deassert m_axi_rx_tvalid even if the frame was originally transmitted without pauses. These pauses are a result of the framing character stripping and left alignment process.
This Figure shows an example of 3n bytes of received data interrupted by a pause. Data is presented on the m_axi_rx_tdata bus. When the first n bytes are placed on the bus, m_axi_rx_tvalid is asserted to indicate that data is ready for the user application. The core deasserts m_axi_rx_tvalid on the clock cycle following the first data beat to indicate a pause in the data flow.
After the pause, the core asserts m_axi_rx_tvalid and continues to assemble the remaining data on the m_axi_rx_tdata bus. At the end of the frame, the core asserts m_axi_rx_tlast. The core also computes the value of m_axi_rx_tkeep bus and presents it to the user application based on the total number of valid bytes in the final word of the frame.
