Full-Duplex Initialization - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID
PG046
Release Date
2023-10-19
Version
11.1 English

Full-duplex cores initialize automatically after power-up, reset, or hard error and perform the Aurora 8B/10B initialization procedure until the channel is ready for use. The lane_up bus indicates which lanes in the channel have finished the lane initialization procedure. This signal can be used to help debug equipment problems in a multi-lane channel. channel_up is asserted only after the core completes the entire initialization procedure.

Aurora 8B/10B cores cannot receive data before channel_up is asserted. Only the m_axi_rx_tvalid signal on the user interface should be used to qualify incoming data. channel_up can be inverted and used to reset modules that drive the TX side of a full-duplex channel, because no transmission can occur until after channel_up. If user application modules need to be reset before data reception, one of the lane_up signals can be inverted and used. Data cannot be received until after all the lane_up signals are asserted.

Note:   The WATCHDOG_TIMEOUT parameter is available in the channel_init_sm module to control the watchdog timers present in the channel initialization process.