The Aurora 8B/10B core top level (block level) file instantiates the lane logic module, TX and RX AXI4-Stream modules, the global logic module, and the wrapper for the transceiver. Also instantiated are the clock, reset circuit, frame generator and checker modules in the example design.
This Figure shows the Aurora 8B/10B core top level for a duplex configuration. The top-level file is the starting point for a user design.
This section provides the streaming and framing interface details. User interface logic should be designed to comply with the timing requirement of the respective interface as explained here.