Transmitting Data - 11.1 English - PG046

To transmit data, the user application manipulates control signals to cause the core to do the following:

• Take data from the user interface on the s_axi_tx_tdata bus when s_axi_tx_tvalid and s_axi_tx_tready signals are asserted.
• Stripe the data across lanes in the Aurora 8B/10B channel.
• Use the s_axi_tx_tvalid signal to transmit data. The user application can deassert s_axi_tx_tvalid to insert idles on the line (introduce stalls or pause).
• Pause data (that is, insert idles) (s_axi_tx_tvalid is deasserted).

When the core receives data, it does the following:

• Detects and discards control bytes (idles, clock compensation, Start of Channel PDU (SCP), End of Channel Protocol Data Unit (ECPDU) and PAD.
• Asserts framing signal (m_axi_rx_tlast) and specifies the number of valid bytes in the last data beat (m_axi_rx_tkeep).
• Recovers data from the lanes.
• Assembles data for presentation to the user interface on the m_axi_rx_tdata bus by asserting of the m_axi_rx_tvalid signal.

The Aurora 8B/10B core samples data only when both s_axi_tx_tready and s_axi_tx_tvalid are asserted (High).

AXI4-Stream data is only valid when it is framed. Data outside of a frame is ignored. To start a frame, assert s_axi_tx_tvalid while the first word of data is on the s_axi_tx_tdata port. To end a frame, assert s_axi_tx_tlast while the last word (or partial word) of data is on the s_axi_tx_tdata port and use s_axi_tx_tkeep to specify the number of valid bytes in the last data beat.

In the case of frames that are a single word long or less, s_axi_tx_tvalid and s_axi_tx_tlast are asserted simultaneously.