Example Design - 11.1 English

Aurora 8B/10B LogiCORE IP Product Guide (PG046)

Document ID

PG046

Release Date

2023-10-19

Version

11.1 English

Each Aurora 8B/10B core includes an example design (<component name>_exdes) that uses the core in a simple data transfer system.

The example design consists these components:

•Frame generator (FRAME_GEN) connected to the TX interface

•Frame checker (FRAME_CHECK) connected to the RX user interface

•VIO/ILA instance for debug and testing

This Figure illustrates the block diagram of the example design for a full-duplex core.

Figure 5-1: Example Design
X-Ref Target - Figure 5-1

The example design uses all of the core interfaces. Simplex cores without a TX or RX interface have no FRAME_GEN or FRAME_CHECK block, respectively.

The FRAME_GEN module generates user traffic to each of the PDU, UFC and NFC interfaces following the AXI4-Stream protocol. This module contains a pseudo-random number generator using a linear feedback shift register (LFSR) with a specific initial value to generate a predictable sequence of data. The FRAME_CHECK module uses this data sequence to verify the integrity of the Aurora data channel. Module inputs are user_clk, reset and channel_up.

The FRAME_CHECK module verifies the integrity of the RX data. This module uses the same LFSR and initial value as the FRAME_GEN module to generate the expected RX frame data. The received user data is compared with the locally-generated stream and any errors are reported per the AXI4-Stream protocol. The FRAME_CHECK module is applicable to PDU, UFC and NFC interfaces.

The example design can be used to quickly get an Aurora 8B/10B design up and running on a board, or perform a quick simulation of the module. The design can also be used as a reference for the connecting the more complicated interfaces of the Aurora 8B/10B core, such as the clocking interface.

When using the example design on a board, be sure to edit the <component name>_
exdes.xdc file to supply the correct pins and clock constraints.

Table: Example Design I/O Ports describes the ports of the example design.

Table 5-1: Example Design I/O Ports
Port	Direction	Clock Domain	Description
rxn[0:m–1]	Input	RX Serial Clock	Negative differential serial data input pin.
rxp[0:m–1]	Input	RX Serial Clock	Positive differential serial data input pin.
txn[0:m–1]	Output	TX Serial Clock	Negative differential serial data output pin.
txp[0:m–1]	Output	TX Serial Clock	Positive differential serial data output pin.
err_count[0:7]	Output	user_clk	Count of the number of data words received by the frame checker that did not match the expected value.
reset	Input	user_clk	Reset signal for the example design. The reset is debounced using a user_clk signal generated from the reference clock input.
gt_reset	Input	init_clk_in	GT Reset signal for the example design. gt_reset is debounced using the init_clk_in signal.
<reference clock(s)>	Input	-	The reference clocks for the Aurora 8B/10B core are brought to the top level of the example design. See Serial Transceiver Reference Clock Interface for details about the reference clocks.
<core error signals>⁽¹⁾	Output	user_clk	The error signals from the Aurora 8B/10B core Status and Control interface are brought to the top level of the example design and registered.
<core channel up signals>⁽¹⁾	Output	user_clk	The channel up status signals for the core are brought to the top level of the example design and registered. Full-duplex cores have a single channel up signal; simplex cores have one for each channel direction supported.
<core lane up signals>⁽¹⁾	Output	user_clk	The lane up status signals for the core are brought to the top level of the example design and registered. Cores have a lane up signal for each GTP or GTX transceiver they use. Simplex cores have a separate lane up signal per GTP or GTX transceiver they use for each channel direction supported.
<simplex initialization signals>⁽¹⁾	Input/ Output	user_clk	If the core is a simplex core, its sideband initialization ports are registered and brought to the top level of the example design.
Notes: 1.See Status, Control, and the Transceiver Interface for details.