Clock Interface - 11.1 English

The clock interface has ports for the transceiver reference clock, and parallel clocks that the Aurora 8B/10B core shares with application logic.

Table: Clock Ports for Aurora 8B/10B Core describes the Aurora 8B/10B core clock ports.

Table 2-15: Clock Ports for Aurora 8B/10B Core
Clock Ports	Direction	Description
pll_not_locked	Input	If a PLL is used to generate clocks for the Aurora 8B/10B core, the pll_not_locked signal should be connected to the inverse of the locked signal of the PLL. If the PLL is not used to generate clock signals for the Aurora 8B/10B core, tie pll_not_locked to ground.
user_clk	Input	Parallel clock shared by the Aurora 8B/10B core and the user application. user_clk and sync_clk are the outputs of a PLL or BUFG driven by tx_out_clk. These clock generations are available in the <component name>_clock_module file. The user_clk goes as the txusrclk2 input to the transceiver.
sync_clk	Input	Parallel clock used by the internal synchronization logic of the transceivers. sync_clk goes as the txusrclk input to the transceiver.
gt_refclk	Input	The gt_refclk (clkp/clkn) port is a dedicated external transceiver reference clock fed through IBUFDS_GTE.
gt0_pll0outclk_in/ gt1_pll0outclk_in	Input	This port should be connected to the PLL0OUTCLK/PLL1OUTCLK clock output generated by GTPE2_COMMON. This port is internally connected to the PLL0CLK/PLL1CLK port on the GTPE2_CHANNEL primitive.
gt0_pll0outrefclk_in/ gt0_pll1outrefclk_in	Input	This port should be connected to the PLL0OUTREFCLK/PLL1OUTREFCLK clock output generated by GTPE2_COMMON. This port is internally connected to the PLL0REFCLK/PLL1REFCLK port on the GTPE2_CHANNEL primitive.
quad1_common_lock_in	Input	GTPE2_COMMON PLL lock input port.

Table: Port Changes Due to Shared Logic Option provides details about the port changes due to selection of the Shared Logic option.

Table 2-16: Port Changes Due to Shared Logic Option
Name	Direction	Description	Remarks
gt_refclk1_p gt_refclk1_n	Input	Transceiver reference clock 1	Enabled when Shared Logic in core is selected. The Single Ended GT REFCLK option gives a single-ended gtrefclk1 input.
gt_refclk2_p gt_refclk2_n	Input	Transceiver reference clock 2	Enabled when Shared Logic in core is selected. The Single Ended GT REFCLK option gives a single ended gtrefclk2 input.
gt_refclk1_out	Output	Output of IBUFDS_GTE2 for transceiver reference clock 1	Enabled when Shared Logic in core is selected. Not available for the Single Ended GT REFCLK option.
gt_refclk2_out	Output	Output of IBUFDS_GTE2 for transceiver reference clock 2	Enabled when Shared Logic in core is selected. Not available for the Single Ended GT REFCLK option.
user_clk_out	Output	Parallel clock shared by Aurora 8B/10B core	Enabled when Shared Logic in core is selected
sync_clk_out	Output	txusrclk for Artix™ 7 device GTP transceiver designs	Enabled when Shared Logic in core is selected
sys_reset_out	Output	Output of de-bouncer for reset	Enabled when Shared Logic in core is selected
gt_reset_out	Output	Output of de-bouncer for gt_reset	Enabled when Shared Logic in core is selected
init_clk_p init_clk_n	Input	Free running system/board clock	Enabled when Shared Logic in core is selected. The Single Ended INIT CLK option provides a single ended init_clk input.
init_clk_out	Output	Output of system clock differential buffer	Enabled when Shared Logic in core is selected. Not available for the Single Ended INIT CLK option.
gt0_pll0refclklost_out gt1_pll0refclklost_out⁽¹⁾	Output	Indicates refclklost port of the GTPE2_COMMON	Enabled when Shared Logic in core is selected.
quad1_common_lock_out quad2_common_lock_out⁽¹⁾	Output	Indicates PLL of the GTPE2_COMMON is achieved lock	Enabled when Shared Logic in core is selected.
gt0_pll0outclk_out gt0_pll1outclk_out gt0_pll0outrefclk_out gt0_pll1outrefclk_out gt1_pll0outclk_out gt1_pll1outclk_out gt1_pll0outrefclk_out gt1_pll1outrefclk_out⁽¹⁾	Output	Clock outputs generated by GTPE2_COMMON	Enabled when Shared Logic in core is selected.
gt<quad>_qplllock_out⁽²⁾⁽³⁾	Output	Indicates PLL of the GTXE2_COMMON/GTHE2_ COMMON has achieved lock	Enabled when Shared Logic in core is selected.
gt<quad>_qpllrefclklost _out⁽²⁾⁽³⁾	Output	Indicates reference clock input to the GTXE2_COMMON/GTHE2_ COMMON is lost	Enabled when Shared Logic in core is selected.
gt_qpllclk_quad<quad>_out gt_qpllclk_quad<quad> _out⁽²⁾⁽³⁾	Output	Clock outputs generated by GTXE2_COMMON/GTHE2_ COMMON	Enabled when Shared Logic in core is selected.
gt_qpllrefclk_quad<quad>_out	Output	Quad phase-locked loop (QPLL) reference clock output generated by the GTXE2_COMMON/GTHE2_COMMON	Enabled when Shared Logic in core is selected.
gt<quad>_qplllock_in	Input	Indicates PLL of the GTXE2_COMMON/GTHE2_ COMMON has achieved lock	Enabled when Shared Logic in example design is selected.
gt<quad>_qpllrefclklost_in	Input	Indicates that the reference clock input to the GTXE2_COMMON/GTHE2_ COMMON is lost	Enabled when Shared Logic in example design is selected.
gt_qpllclk_quad<quad>_in	Input	Clock outputs generated from the GTXE2_COMMON/GTHE2_COMMON	Enabled when Shared Logic in example design is selected.
gt_qpllrefclk_quad<quad>_ in	Input	QPLL reference clock output generated from the GTXE2_COMMON/GTHE2_COMMON	Enabled when Shared Logic in example design is selected.
gt_qpllreset_out	Output	Tied to ground	Enabled when Shared Logic in example design is selected.
tx_out_clk	Output	Parallel clock shared by Aurora 8B/10B core	Enabled when Shared Logic in example design is selected.
Notes: 1.Ports from GTPE2_COMMON are applicable only to Artix 7 FPGA GTP transceiver designs. 2.Ports from GTXE2_COMMON/GTHE2_COMMON are applicable only to 7 series FPGA GTX/GTH transceiver designs. 3.These ports are enabled for each selected quad. <quad> refers to the transceiver quad numbered from 1 to 12.