These documents provide supplemental material useful with this product guide. You should be familiar with these documents prior to generating an Aurora 8B/10B core.
- UltraScale Architecture GTH Transceivers User Guide (UG576)
- 7 Series FPGAs GTP Transceivers User Guide (UG482)
- 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
- AMBA AXI4-Stream Protocol Specification (v1.0)
- Aurora 8B/10B Protocol Specification (SP002)
- Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
- Vivado Design Suite User Guide: Designing with IP (UG896)
- Vivado Design Suite User Guide: Getting Started (UG910)
- Vivado Design Suite User Guide: Logic Simulation (UG900)
- Designing a System Using the Aurora 8B10B Core (Duplex) on the KC705 Evaluation Kit (XAPP1193)
- Vivado Design Suite User Guide: Programming and Debugging (UG908)
- UltraScale Architecture Migration: Methodology Guide (UG1026)
- LogiCORE IP Aurora 8B/10B v5.3 Data Sheet (DS637)
- LogiCORE IP Aurora 8B/10B v5.3 User Guide (UG353)
- Packaging Custom AXI IP for Vivado IP Integrator Application Note (XAPP1168
- UltraScale FPGAs Transceivers Wizard LogiCORE IP Product Guide (PG182)
- 7 Series FPGAs Data Sheet: Overview (DS180)
- UltraScale Architecture and Product Data Sheet: Overview (DS890)
- Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
- Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
- Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
- Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
- Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)