IOBUFDS_DIFF_OUT - 2024.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)
Document ID
UG953
Release Date
2024-11-13
Version
2024.2 English

Primitive: Differential Bi-directional Buffer with Differential Output

Introduction

This design element is a bidirectional buffer that supports low-voltage, differential signaling. For the IOBUFDS_DIFF_OUT, a design level interface signal is represented as two distinct ports (IO and IOB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and MYNET_N). The IOBUFDS_DIFF_OUT differs from the IOBUFDS in that it allows internal access to both phases of the differential signal. Optionally, a programmable differential termination feature is available to help improve signal integrity and reduce external components.

Port Descriptions

Port Direction Width Function
O Output 1 Buffer p-side output.
OB Output 1 Buffer n-side output.
IO In/out 1 Diff_p In/out (connect directly to top-level port).
IOB In/out 1 Diff_n In/out (connect directly to top-level port).
I Input 1 Buffer input.
TM Input 1 3-state enable input from master OLOGIC, high=input, low=output.
TS Input 1 3-state enable input from slave OLOGIC, high=input, low=output.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DIFF_TERM BOOLEAN TRUE, FALSE FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR BOOLEAN TRUE, FALSE TRUE When set to TRUE, allows for reduced power when using differential or referenced (requiring VREF) input standards like LVDS or HSTL. A setting of FALSE demands more power but delivers higher performance characteristics. Consult the7 Series FPGA SelectIO Resources User Guide (UG471) for details.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Diffirential Output
--                   7 Series
-- Xilinx HDL Language Template, version 2024.2

IOBUFDS_DIFF_OUT_inst : IOBUFDS_DIFF_OUT
generic map (
   DIFF_TERM => FALSE, -- Differential Termination (TRUE/FALSE)
   IBUF_LOW_PWR => TRUE, -- Low Power - TRUE, High Performance = FALSE
   IOSTANDARD => "BLVDS_25") -- Specify the I/O standard
port map (
   O => O,     -- Buffer p-side output
   OB => OB,   -- Buffer n-side output
   IO => IO,   -- Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- Diff_n inout (connect directly to top-level port)
   I => I,     -- Buffer input
   TM => TM,   -- 3-state enable input, high=input, low=output
   TS => TS    -- 3-state enable input, high=input, low=output
);

-- End of IOBUFDS_DIFF_OUT_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT: Differential Bi-directional Buffer with Differential Output
//                   7 Series
// Xilinx HDL Language Template, version 2024.2

IOBUFDS_DIFF_OUT #(
   .DIFF_TERM("FALSE"),    // Differential Termination ("TRUE"/"FALSE")
   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("BLVDS_25") // Specify the I/O standard
) IOBUFDS_DIFF_OUT_inst (
   .O(O),     // Buffer p-side output
   .OB(OB),   // Buffer n-side output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .I(I),     // Buffer input
   .TM(TM),   // 3-state enable input, high=input, low=output
   .TS(TS)    // 3-state enable input, high=input, low=output
);

// End of IOBUFDS_DIFF_OUT_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)