BUFIO - 2024.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2024-05-30
Version
2024.1 English

Primitive: Local Clock Buffer for I/O

Introduction

This design element is a local clock-in, clock-out buffer. It drives a dedicated clock net within the I/O column, independent of the global clock resources and is ideally suited for source-synchronous data capture (forwarded/receiver clock distribution). BUFIO elements can be driven by a dedicated MRCC I/O located in the same clock region, or a BUFMRCE/BUFMR component capable of clocking multiple clock regions. BUFIO can only drive I/O components within the bank in which they exist. They cannot directly drive logic resources (CLB, block RAM, etc.) because the I/O clock network only reaches the I/O column.

Port Descriptions

Port Direction Width Function
I Input 1 Input port to clock buffer. Connect this to an IBUF connected to a top-level port or an associated BUFMR buffer.
O Output 1 Output port from clock buffer. Connect this to the clock inputs to synchronous I/O components like the ISERDESE2, OSERDESE2, IDDR, ODDR or register connected directly to an I/O port (inferred or instantiated).

Design Entry Method

Instantiation Yes
Inference No
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFIO: Local Clock Buffer for I/O
--        7 Series
-- Xilinx HDL Language Template, version 2024.1

BUFIO_inst : BUFIO
port map (
   O => O, -- 1-bit output: Clock output (connect to I/O clock loads).
   I => I  -- 1-bit input: Clock input (connect to an IBUF or BUFMR).
);

-- End of BUFIO_inst instantiation

Verilog Instantiation Template


// BUFIO: Local Clock Buffer for I/O
//        7 Series
// Xilinx HDL Language Template, version 2024.1

BUFIO BUFIO_inst (
   .O(O), // 1-bit output: Clock output (connect to I/O clock loads).
   .I(I)  // 1-bit input: Clock input (connect to an IBUF or BUFMR).
);

// End of BUFIO_inst instantiation

Related Information

  • 7 Series FPGAs Clocking Resources User Guide (UG472)