Primitive: Output SERial/DESerializer with bitslip
Introduction
The OSERDESE2 is a dedicated parallel-to-serial converter with specific clocking and logic resources designed to facilitate the implementation of high-speed source-synchronous interfaces. Every OSERDESE2 module includes a dedicated serializer for data and 3-state control. Both data and 3-state serializers can be configured in single data rate (SDR) and double data rate (DDR) mode. Data serialization can be up to 8:1 (10:1 or 14:1 if using OSERDESE2 Width Expansion). 3-state serialization can be up to 4:1.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CLK | Input | 1 | A high speed clock input that drives the serial side of the parallel-to-serial converters. |
| CLKDIV | Input | 1 | A divided high-speed clock input that drives the parallel side of the parallel-to-serial converters. This clock is the divided version of the clock connected to the CLK port. |
| D1 - D8 | Input | 1 | Incoming parallel data enters the module through ports D1 to D8. These ports are connected to the FPGA fabric, and can be configured from two to eight bits (i.e., a 8:1 serialization). Bit widths greater than six (up to 14) can be supported by using a second OSERDESE2 in SLAVE mode. |
| OCE | Input | 1 | OCE is an active-High clock enable for the data path. |
| OFB | Output | 1 | The output feedback port (OFB) is the serial (high-speed) data output port of the OSERDESE2. |
| OQ | Output | 1 | The OQ port is the data output port of the module. Data at the input port D1 will appear first at OQ. This port connects the output of the data parallel-to-serial converter to the data input of the IOB. This port can not drive the ODELAYE2; the OFB pin must be used. |
| RST | Input | 1 | The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains to be driven Low asynchronously. OSERDESE2 circuits running in the CLK domain where timing is critical use an internal, dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLK domain. Similarly, there is a dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLKDIV domain. Because there are OSERDESE2 circuits that retime the RST input, you only need to provide a reset pulse to the RST input that meets timing on the CLKDIV frequency domain (synchronous to CLKDIV). Therefore, RST should be driven High for a minimum of one CLKDIV cycle. When building an interface consisting of multiple OSERDESE2 ports, all ports must be synchronized. The internal retiming of the RST input is designed so that all OSERDESE2 blocks that receive the same reset pulse come out of reset synchronized with one another. |
| SHIFTIN1 / SHIFTIN2 | Input | 1 | Cascade Input for data input expansion. Connect to SHIFTOUT1/2 of slave. |
| SHIFTOUT1 / SHIFTOUT2 | Output | 1 | Cascade out for data input expansion. Connect to SHIFTIN1/2 of master. |
| TBYTEIN | Input | 1 | Byte group tristate input from source |
| TBYTEOUT | Output | 1 | Byte group tristate output to IOB |
| TCE | Input | 1 | Active-High clock enable for the 3-state control path. |
| TFB | Output | 1 | 3-state control output of the module sent to the ODELAYE2. When used, this port connects the output of the 3-state parallel-to-serial converter to the control/3-state input of the ODELAYE2. |
| TQ | Output | 1 | This port is the 3-state control output of the module. When used, this port connects the output of the 3-state parallel-to-serial converter to the control/3-state input of the IOB. |
| T1 - T4 | Input | 1 | Parallel 3-state signals enter the module through ports T1 to T4. The ports are connected to the FPGA fabric, and can be configured as one, two, or four bits. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP Catalog | Yes |
| Macro support | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| DATA_RATE_OQ | STRING | "DDR", "SDR" | "DDR" | Defines whether data is processed as single data rate (SDR) or double data rate (DDR). |
| DATA_RATE_TQ | STRING | "DDR", "BUF", "SDR" | "DDR" | Defines whether 3-state control is to be processed as single data rate (SDR) or double data rate (DDR). |
| DATA_WIDTH | DECIMAL | 4, 2, 3, 5, 6, 7, 8, 10, 14 | 4 | Defines the parallel data input width of the parallel-to-serial converter. Possible values depend on the DATA_RATE_OQ attribute. When DATA_RATE_OQ is SDR, possible values are 2, 3, 4, 5, 6, 7, and 8. When DATA_RATE_OQ is DDR, the possible values for the DATA_WIDTH attribute are 4, 6, 8, 10 and 14. When DATA_WIDTH is larger than eight, a pair of OSERDESE2 must be configured into a master-slave configuration. |
| INIT_OQ | BINARY | 1'b0 to 1'b1 | 1'b0 | Defines the initial value of OQ output. |
| INIT_TQ | BINARY | 1'b0 to 1'b1 | 1'b0 | Defines the initial value of TQ output. |
| SERDES_MODE | STRING | "MASTER", "SLAVE" | "MASTER" | Defines whether the module is a master or slave when using width expansion. |
| SRVAL_OQ | BINARY | 1'b0 to 1'b1 | 1'b0 | Defines the value of OQ outputs when the SR is invoked. |
| SRVAL_TQ | BINARY | 1'b0 to 1'b1 | 1'b0 | Defines the value of YQ outputs when the SR is invoked. |
| TBYTE_CTL | STRING | "FALSE", "TRUE" | "FALSE" | Enable Tristate BYTE operation for DDR3 mode. This allows the tristate signal to take value from one of the tristate outputs which is acting as a source. |
| TBYTE_SRC | STRING | "FALSE", "TRUE" | "FALSE" | Enable OSERDESE2 to act as a source for Tristate Byte operation in DDR3 mode. |
| TRISTATE_WIDTH | DECIMAL | 4, 1 | 4 | Defines the parallel 3-state input width of the 3-state control parallel-to-serial converter. Possible values depend on the DATA_RATE_TQ attribute. When DATA_RATE_TQ is SDR or BUF, the TRISTATE_WIDTH attribute can only be set to 1. When DATA_RATE_TQ = DDR, the possible values for the TRISTATE_WIDTH attribute is 4. TRISTATE_WIDTH cannot be set to widths larger than 4. When a DATA_WIDTH is larger than four, set the TRISTATE_WIDTH to 1. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OSERDESE2: Output SERial/DESerializer with bitslip
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
OSERDESE2_inst : OSERDESE2
generic map (
DATA_RATE_OQ => "DDR", -- DDR, SDR
DATA_RATE_TQ => "DDR", -- DDR, BUF, SDR
DATA_WIDTH => 4, -- Parallel data width (2-8,10,14)
INIT_OQ => '0', -- Initial value of OQ output (1'b0,1'b1)
INIT_TQ => '0', -- Initial value of TQ output (1'b0,1'b1)
SERDES_MODE => "MASTER", -- MASTER, SLAVE
SRVAL_OQ => '0', -- OQ output value when SR is used (1'b0,1'b1)
SRVAL_TQ => '0', -- TQ output value when SR is used (1'b0,1'b1)
TBYTE_CTL => "FALSE", -- Enable tristate byte operation (FALSE, TRUE)
TBYTE_SRC => "FALSE", -- Tristate byte source (FALSE, TRUE)
TRISTATE_WIDTH => 4 -- 3-state converter width (1,4)
)
port map (
OFB => OFB, -- 1-bit output: Feedback path for data
OQ => OQ, -- 1-bit output: Data path output
-- SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
SHIFTOUT1 => SHIFTOUT1,
SHIFTOUT2 => SHIFTOUT2,
TBYTEOUT => TBYTEOUT, -- 1-bit output: Byte group tristate
TFB => TFB, -- 1-bit output: 3-state control
TQ => TQ, -- 1-bit output: 3-state control
CLK => CLK, -- 1-bit input: High speed clock
CLKDIV => CLKDIV, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => D1,
D2 => D2,
D3 => D3,
D4 => D4,
D5 => D5,
D6 => D6,
D7 => D7,
D8 => D8,
OCE => OCE, -- 1-bit input: Output data clock enable
RST => RST, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => SHIFTIN1,
SHIFTIN2 => SHIFTIN2,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => T1,
T2 => T2,
T3 => T3,
T4 => T4,
TBYTEIN => TBYTEIN, -- 1-bit input: Byte group tristate
TCE => TCE -- 1-bit input: 3-state clock enable
);
-- End of OSERDESE2_inst instantiation
Verilog Instantiation Template
// OSERDESE2: Output SERial/DESerializer with bitslip
// 7 Series
// Xilinx HDL Language Template, version 2024.1
OSERDESE2 #(
.DATA_RATE_OQ("DDR"), // DDR, SDR
.DATA_RATE_TQ("DDR"), // DDR, BUF, SDR
.DATA_WIDTH(4), // Parallel data width (2-8,10,14)
.INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
.INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
.SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1)
.SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1)
.TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE)
.TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE)
.TRISTATE_WIDTH(4) // 3-state converter width (1,4)
)
OSERDESE2_inst (
.OFB(OFB), // 1-bit output: Feedback path for data
.OQ(OQ), // 1-bit output: Data path output
// SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
.SHIFTOUT1(SHIFTOUT1),
.SHIFTOUT2(SHIFTOUT2),
.TBYTEOUT(TBYTEOUT), // 1-bit output: Byte group tristate
.TFB(TFB), // 1-bit output: 3-state control
.TQ(TQ), // 1-bit output: 3-state control
.CLK(CLK), // 1-bit input: High speed clock
.CLKDIV(CLKDIV), // 1-bit input: Divided clock
// D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.D5(D5),
.D6(D6),
.D7(D7),
.D8(D8),
.OCE(OCE), // 1-bit input: Output data clock enable
.RST(RST), // 1-bit input: Reset
// SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
.SHIFTIN1(SHIFTIN1),
.SHIFTIN2(SHIFTIN2),
// T1 - T4: 1-bit (each) input: Parallel 3-state inputs
.T1(T1),
.T2(T2),
.T3(T3),
.T4(T4),
.TBYTEIN(TBYTEIN), // 1-bit input: Byte group tristate
.TCE(TCE) // 1-bit input: 3-state clock enable
);
// End of OSERDESE2_inst instantiation
Related Information
- 7 Series FPGAs SelectIO Resources User Guide (UG471)