MULT_MACRO - 2024.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2024-05-30
Version
2024.1 English

Macro: Multiplier

Introduction

MULT_MACRO simplifies the instantiation of the DSP48 block when used as a simple signed multiplier. It features parameterizable input and output widths and latencies that ease the integration of the DSP48 block into HDL.

Port Descriptions

Port Direction Width Function
P Output Variable, equals WIDTH_A + WIDTH_B. Primary data output.
A Input Variable, see WIDTH_A attribute. Multiplier data input.
B Input Variable, see WIDTH_B attribute. Multiplier data input.
CE Input 1 Clock Enable.
CLK Input 1 Clock.
RST Input 1 Synchronous Reset.

Design Entry Method

This unimacro is a parameterizable version of the primitive, and can be instantiated only.
Instantiation Yes
Inference No
IP Catalog No
Macro support Recommended

Available Attributes

Attribute Type Allowed Values Default Description
DEVICE STRING "7SERIES" "7SERIES" Target hardware architecture.
WIDTH_A INTEGER 1 to 25 18 Multiplier A-input bus width.
WIDTH_B INTEGER 1 to 18 18 Multiplier B-input bus width.
LATENCY INTEGER 0, 1, 2, 3, 4 3 Number of pipeline registers.
  • 1: MREG == 1
  • 2: AREG == BREG == 1 and MREG == 1 or MREG == 1 and PREG == 1
  • 3: AREG == BREG == 1 and MREG == 1 and PREG == 1
  • 4: AREG == BREG == 2 and MREG == 1 and PREG == 1

VHDL Instantiation Template

Unless they already exist, copy the following four statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;

-- MULT_MACRO: Multiply Function implemented in a DSP48E
--             7 Series
-- Xilinx HDL Language Template, version 2024.1

MULT_MACRO_inst : MULT_MACRO
generic map (
   DEVICE => "7SERIES",    -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
   LATENCY => 3,           -- Desired clock cycle latency, 0-4
   WIDTH_A => 18,          -- Multiplier A-input bus width, 1-25
   WIDTH_B => 18)          -- Multiplier B-input bus width, 1-18
port map (
   P => P,     -- Multiplier ouput bus, width determined by WIDTH_P generic
   A => A,     -- Multiplier input A bus, width determined by WIDTH_A generic
   B => B,     -- Multiplier input B bus, width determined by WIDTH_B generic
   CE => CE,   -- 1-bit active high input clock enable
   CLK => CLK, -- 1-bit positive edge clock input
   RST => RST  -- 1-bit input active high reset
);
-- End of MULT_MACRO_inst instantiation

Verilog Instantiation Template


// MULT_MACRO: Multiply Function implemented in a DSP48E
//             7 Series
// Xilinx HDL Language Template, version 2024.1

MULT_MACRO #(
   .DEVICE("7SERIES"), // Target Device: "7SERIES"
   .LATENCY(3),        // Desired clock cycle latency, 0-4
   .WIDTH_A(18),       // Multiplier A-input bus width, 1-25
   .WIDTH_B(18)        // Multiplier B-input bus width, 1-18
) MULT_MACRO_inst (
   .P(P),     // Multiplier output bus, width determined by WIDTH_P parameter
   .A(A),     // Multiplier input A bus, width determined by WIDTH_A parameter
   .B(B),     // Multiplier input B bus, width determined by WIDTH_B parameter
   .CE(CE),   // 1-bit active high input clock enable
   .CLK(CLK), // 1-bit positive edge clock input
   .RST(RST)  // 1-bit input active high reset
);

// End of MULT_MACRO_inst instantiation