Primitive: Global Clock Mux Buffer with Output State 1
Introduction
This design element is a global clock buffer, based on BUFGCTRL, that can select between two input clocks: I0 and I1. When the select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on I1 is selected for output. BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when it switches between clocks in response to a change in the select input. BUFGMUX assumes output state 0 and BUFGMUX_1 assumes output state 1.
Logic Table
| Inputs | Outputs | ||
|---|---|---|---|
| I0 | I1 | S | O |
| I0 | X | 0 | I0 |
| X | I1 | 1 | I1 |
| X | X | ↑ | 1 |
| X | X | ↓ | 1 |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGMUX_1: Global Clock Mux Buffer with Output State 1
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
BUFGMUX_1_inst : BUFGMUX_1
port map (
O => O, -- 1-bit output: Clock output
I0 => I0, -- 1-bit input: Clock input (S=0)
I1 => I1, -- 1-bit input: Clock input (S=1)
S => S -- 1-bit input: Clock select
);
-- End of BUFGMUX_1_inst instantiation
Verilog Instantiation Template
// BUFGMUX_1: Global Clock Mux Buffer with Output State 1
// 7 Series
// Xilinx HDL Language Template, version 2024.1
BUFGMUX_1 #(
)
BUFGMUX_1_inst (
.O(O), // 1-bit output: Clock output
.I0(I0), // 1-bit input: Clock input (S=0)
.I1(I1), // 1-bit input: Clock input (S=1)
.S(S) // 1-bit input: Clock select
);
// End of BUFGMUX_1_inst instantiation
Related Information
- 7 Series FPGAs Clocking Resources User Guide (UG472)