Primitive: Global Clock Buffer with Clock Enable
Introduction
This design element is a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.
Logic Table
| Inputs | Outputs | |
|---|---|---|
| I | CE | O |
| X | 0 | 0 |
| I | 1 | I |
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CE | Input | 1 | Clock buffer active-High enable. |
| I | Input | 1 | Clock input. |
| O | Output | 1 | Clock output. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE: Global Clock Buffer with Clock Enable
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
BUFGCE_inst : BUFGCE
port map (
O => O, -- 1-bit output: Clock output
CE => CE, -- 1-bit input: Clock enable input for I0
I => I -- 1-bit input: Primary clock
);
-- End of BUFGCE_inst instantiation
Verilog Instantiation Template
// BUFGCE: Global Clock Buffer with Clock Enable
// 7 Series
// Xilinx HDL Language Template, version 2024.1
BUFGCE BUFGCE_inst (
.O(O), // 1-bit output: Clock output
.CE(CE), // 1-bit input: Clock enable input for I0
.I(I) // 1-bit input: Primary clock
);
// End of BUFGCE_inst instantiation
Related Information
- 7 Series FPGAs Clocking Resources User Guide (UG472)