Primitive: Input First-In, First-Out (FIFO)
Introduction
The Input FIFO is a new resource located next to the I/O. This dedicated hardware is designed to help transition the data from the input port, input register, IDDR, or ISERDESE2 to the fabric. It has two basic modes. The first is a 4x4 mode where the data coming into the FIFO goes out at the same rate. The second mode is a 4x8 mode where the data coming out is de-serialized by a factor of 2. In other words in 4x8 mode 4-bits go to the IN_FIFO and 8-bits come out. Features of this component include:
- Array dimensions: 80 wide, 8 deep (4x8 mode); 40 wide, 8 deep (4x4 mode)
- Empty and Full flags
- Programmable Almost Empty and Almost Full flags
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
ALMOSTEMPTY | Output | 1 | Active-High output flag indicating the FIFO is almost empty. The threshold of the almost empty flag is set by the ALMOST_EMPTY_VALUE attribute. |
ALMOSTFULL | Output | 1 | Active-High output flag indicating the FIFO is almost full. The threshold of the almost empty flag is set by the ALMOST_FULL_VALUE attribute. |
D0<3:0> | Input | 4 | Channel 0 input bus. |
D1<3:0> | Input | 4 | Channel 1 input bus. |
D2<3:0> | Input | 4 | Channel 2 input bus. |
D3<3:0> | Input | 4 | Channel 3 input bus. |
D4<3:0> | Input | 4 | Channel 4 input bus. |
D5<7:0> | Input | 8 | Channel 5 input bus. |
D6<7:0> | Input | 8 | Channel 6 input bus. |
D7<3:0> | Input | 4 | Channel 7 input bus. |
D8<3:0> | Input | 4 | Channel 8 input bus. |
D9<3:0> | Input | 4 | Channel 9 input bus. |
EMPTY | Output | 1 | Active-High output flag indicating the FIFO is empty. |
FULL | Output | 1 | Active-High output flag indicating the FIFO is full. |
Q0<7:0> | Output | 8 | Channel 0 input bus. |
Q1<7:0> | Output | 8 | Channel 1 output bus. |
Q2<7:0> | Output | 8 | Channel 2 output bus. |
Q3<7:0> | Output | 8 | Channel 3 output bus. |
Q4<7:0> | Output | 8 | Channel 4 output bus. |
Q5<7:0> | Output | 8 | Channel 5 output bus. |
Q6<7:0> | Output | 8 | Channel 6 output bus. |
Q7<7:0> | Output | 8 | Channel 7 output bus. |
Q8<7:0> | Output | 8 | Channel 8 output bus. |
Q9<7:0> | Output | 8 | Channel 9 output bus. |
RDCLK | Input | 1 | Read clock. |
RDEN | Input | 1 | Active-High read enable. |
RESET | Input | 1 | Active-High asynchronous reset. |
WRCLK | Input | 1 | Write clock. |
WREN | Input | 1 | Active-High write enable. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
ALMOST_EMPTY _VALUE | DECIMAL | 1, 2 | 1 | Specifies the number of entries left before asserting the ALMOSTEMPTY output signal. |
ALMOST_FULL _VALUE | DECIMAL | 1, 2 | 1 | Specifies the number of entries left before asserting the ALMOSTFULL output signal. |
ARRAY_MODE | STRING | "ARRAY_MODE_4_X_8", "ARRAY_MODE_4_X_4" | "ARRAY_MODE_4_X_8" | Specifies deserializer mode:
|
SYNCHRONOUS _MODE | STRING | "FALSE" | "FALSE" | Specify whether the RDCLK and WRCLK are synchronous to each other. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IN_FIFO: Input First-In, First-Out (FIFO)
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
IN_FIFO_inst : IN_FIFO
generic map (
ALMOST_EMPTY_VALUE => 1, -- Almost empty offset (1-2)
ALMOST_FULL_VALUE => 1, -- Almost full offset (1-2)
ARRAY_MODE => "ARRAY_MODE_4_X_8", -- ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
SYNCHRONOUS_MODE => "FALSE" -- Clock synchronous (FALSE)
)
port map (
-- FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output: Almost empty
ALMOSTFULL => ALMOSTFULL, -- 1-bit output: Almost full
EMPTY => EMPTY, -- 1-bit output: Empty
FULL => FULL, -- 1-bit output: Full
-- Q0-Q9: 8-bit (each) output: FIFO Outputs
Q0 => Q0, -- 8-bit output: Channel 0
Q1 => Q1, -- 8-bit output: Channel 1
Q2 => Q2, -- 8-bit output: Channel 2
Q3 => Q3, -- 8-bit output: Channel 3
Q4 => Q4, -- 8-bit output: Channel 4
Q5 => Q5, -- 8-bit output: Channel 5
Q6 => Q6, -- 8-bit output: Channel 6
Q7 => Q7, -- 8-bit output: Channel 7
Q8 => Q8, -- 8-bit output: Channel 8
Q9 => Q9, -- 8-bit output: Channel 9
-- D0-D9: 4-bit (each) input: FIFO inputs
D0 => D0, -- 4-bit input: Channel 0
D1 => D1, -- 4-bit input: Channel 1
D2 => D2, -- 4-bit input: Channel 2
D3 => D3, -- 4-bit input: Channel 3
D4 => D4, -- 4-bit input: Channel 4
D5 => D5, -- 8-bit input: Channel 5
D6 => D6, -- 8-bit input: Channel 6
D7 => D7, -- 4-bit input: Channel 7
D8 => D8, -- 4-bit input: Channel 8
D9 => D9, -- 4-bit input: Channel 9
-- FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
RDCLK => RDCLK, -- 1-bit input: Read clock
RDEN => RDEN, -- 1-bit input: Read enable
RESET => RESET, -- 1-bit input: Reset
WRCLK => WRCLK, -- 1-bit input: Write clock
WREN => WREN -- 1-bit input: Write enable
);
-- End of IN_FIFO_inst instantiation
Verilog Instantiation Template
// IN_FIFO: Input First-In, First-Out (FIFO)
// 7 Series
// Xilinx HDL Language Template, version 2024.1
IN_FIFO #(
.ALMOST_EMPTY_VALUE(1), // Almost empty offset (1-2)
.ALMOST_FULL_VALUE(1), // Almost full offset (1-2)
.ARRAY_MODE("ARRAY_MODE_4_X_8"), // ARRAY_MODE_4_X_8, ARRAY_MODE_4_X_4
.SYNCHRONOUS_MODE("FALSE") // Clock synchronous (FALSE)
)
IN_FIFO_inst (
// FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full
.EMPTY(EMPTY), // 1-bit output: Empty
.FULL(FULL), // 1-bit output: Full
// Q0-Q9: 8-bit (each) output: FIFO Outputs
.Q0(Q0), // 8-bit output: Channel 0
.Q1(Q1), // 8-bit output: Channel 1
.Q2(Q2), // 8-bit output: Channel 2
.Q3(Q3), // 8-bit output: Channel 3
.Q4(Q4), // 8-bit output: Channel 4
.Q5(Q5), // 8-bit output: Channel 5
.Q6(Q6), // 8-bit output: Channel 6
.Q7(Q7), // 8-bit output: Channel 7
.Q8(Q8), // 8-bit output: Channel 8
.Q9(Q9), // 8-bit output: Channel 9
// D0-D9: 4-bit (each) input: FIFO inputs
.D0(D0), // 4-bit input: Channel 0
.D1(D1), // 4-bit input: Channel 1
.D2(D2), // 4-bit input: Channel 2
.D3(D3), // 4-bit input: Channel 3
.D4(D4), // 4-bit input: Channel 4
.D5(D5), // 8-bit input: Channel 5
.D6(D6), // 8-bit input: Channel 6
.D7(D7), // 4-bit input: Channel 7
.D8(D8), // 4-bit input: Channel 8
.D9(D9), // 4-bit input: Channel 9
// FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
.RDCLK(RDCLK), // 1-bit input: Read clock
.RDEN(RDEN), // 1-bit input: Read enable
.RESET(RESET), // 1-bit input: Reset
.WRCLK(WRCLK), // 1-bit input: Write clock
.WREN(WREN) // 1-bit input: Write enable
);
// End of IN_FIFO_inst instantiation
Related Information
- 7 Series FPGAs SelectIO Resources User Guide (UG471)