BUFGCTRL - 2024.1 English

Primitive: Global Clock Control Buffer

Introduction

BUFGCTRL primitive is a 7 series global clock buffer that is designed as a synchronous/asynchronous "glitch free" 2:1 multiplexer with two clock inputs. Unlike global clock buffers that are found in previous generations of FPGAs, these clock buffers are designed with more control pins to provide a wider range of functionality and more robust input switching. BUFGCTRL is not limited to clocking applications.

Port Descriptions

Port	Direction	Width	Function
CE0	Input	1	Clock enable input for the I0 clock input. A setup/hold time must be guaranteed when you are using the CE0 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
CE1	Input	1	Clock enable input for the I1 clock input. A setup/hold time must be guaranteed when you are using the CE1 pin to enable this input. Failure to meet this requirement could result in a clock glitch.
IGNORE0	Input	1	Clock ignore input for I0 input. Asserting the IGNORE pin will bypass the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
IGNORE1	Input	1	Clock ignore input for I1 input. Asserting the IGNORE pin will bypass the BUFGCTRL from detecting the conditions for switching between two clock inputs. In other words, asserting IGNORE causes the MUX to switch the inputs at the instant the select pin changes. IGNORE0 causes the output to switch away from the I0 input immediately when the select pin changes, while IGNORE1 causes the output to switch away from the I1 input immediately when the select pin changes.
I0	Input	1	Primary clock input into the BUFGCTRL enabled by the CE0 input and selected by the S0 input.
I1	Input	1	Secondary clock input into the BUFGCTRL enabled by the CE1 input and selected by the S1 input.
O	Output	1	Clock output
S0	Input	1	Clock select input for I0. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.
S1	Input	1	Clock select input for I1. The S pins represent the clock select pin for each clock input. When using the S pin as input select, there is a setup/hold time requirement. Unlike CE pins, failure to meet this requirement will not result in a clock glitch. However, it can cause the output clock to appear one clock cycle later.

Design Entry Method

Instantiation	Recommended
Inference	No
IP Catalog	No
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
INIT_OUT	DECIMAL	0, 1	0	Initializes the BUFGCTRL output to the specified value after configuration.
PRESELECT_I0	BOOLEAN	FALSE, TRUE	FALSE	If TRUE, BUFGCTRL output uses I0 input after configuration.
PRESELECT_I1	BOOLEAN	FALSE, TRUE	FALSE	If TRUE, BUFGCTRL output uses I1 input after configuration.

Note: Both PRESELECT attributes might not be TRUE at the same time.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- BUFGCTRL: Global Clock Control Buffer
--           7 Series
-- Xilinx HDL Language Template, version 2024.1

BUFGCTRL_inst : BUFGCTRL
generic map (
   INIT_OUT => 0,         -- Initial value of BUFGCTRL output ($VALUES;)
   PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input ($VALUES;)
   PRESELECT_I1 => FALSE  -- BUFGCTRL output uses I1 input ($VALUES;)
)
port map (
   O => O,             -- 1-bit output: Clock output
   CE0 => CE0,         -- 1-bit input: Clock enable input for I0
   CE1 => CE1,         -- 1-bit input: Clock enable input for I1
   I0 => I0,           -- 1-bit input: Primary clock
   I1 => I1,           -- 1-bit input: Secondary clock
   IGNORE0 => IGNORE0, -- 1-bit input: Clock ignore input for I0
   IGNORE1 => IGNORE1, -- 1-bit input: Clock ignore input for I1
   S0 => S0,           -- 1-bit input: Clock select for I0
   S1 => S1            -- 1-bit input: Clock select for I1
);

-- End of BUFGCTRL_inst instantiation

Verilog Instantiation Template


// BUFGCTRL: Global Clock Control Buffer
//           7 Series
// Xilinx HDL Language Template, version 2024.1

BUFGCTRL #(
   .INIT_OUT(0),           // Initial value of BUFGCTRL output ($VALUES;)
   .PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input ($VALUES;)
   .PRESELECT_I1("FALSE")  // BUFGCTRL output uses I1 input ($VALUES;)
)
BUFGCTRL_inst (
   .O(O),             // 1-bit output: Clock output
   .CE0(CE0),         // 1-bit input: Clock enable input for I0
   .CE1(CE1),         // 1-bit input: Clock enable input for I1
   .I0(I0),           // 1-bit input: Primary clock
   .I1(I1),           // 1-bit input: Secondary clock
   .IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
   .IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
   .S0(S0),           // 1-bit input: Clock select for I0
   .S1(S1)            // 1-bit input: Clock select for I1
);

// End of BUFGCTRL_inst instantiation

Related Information

7 Series FPGAs Clocking Resources User Guide (UG472)