Primitive: Device DNA Access Port
Introduction
The DNA_PORT allows access to a dedicated shift register that can be loaded with the Device DNA data bits (factory-programmed, read-only ID) for a given 7 Series device. In addition to shifting out the DNA data bits, this component allows for the inclusion of supplemental bits of your data, or allows for the DNA data to rollover (repeat DNA data after initial data has been shifted out). This component is primarily used with other circuitry to build added copy protection for the FPGA bitstream from possible theft. Connect all inputs and outputs to the design to ensure proper operation.
To access the Device DNA data, first load the shift register by setting the active-High READ signal for one clock cycle. After the shift register is loaded, the data can be synchronously shifted out by enabling the active-High SHIFT input and capturing the data out the DOUT output port. Additional data can be appended to the end of the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data rollover is desired, connect the DOUT port directly to the DIN port to allow for the same data to be shifted out after completing the 57-bit shift operation. If no additional data is necessary, the DIN port can be tied to a logic zero. The attribute SIM_DNA_VALUE can be optionally set to allow for simulation of a possible DNA data sequence. By default, the Device DNA data bits are all zeros in the simulation model.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
CLK | Input | 1 | Clock input. |
DIN | Input | 1 | User data input pin. |
DOUT | Output | 1 | DNA output data. |
READ | Input | 1 | Active-High load DNA, active-Low read input. |
SHIFT | Input | 1 | Active-High shift enable input. |
Design Entry Method
Instantiation | Recommended |
Inference | No |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
SIM_DNA_VALUE | HEX | 57-bit HEX value | All zeros | Specifies a sample 57-bit DNA value for simulation. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- DNA_PORT: Device DNA Access Port
-- 7 Series
-- Xilinx HDL Language Template, version 2024.2
DNA_PORT_inst : DNA_PORT
generic map (
SIM_DNA_VALUE => X"000000000000000" -- Specifies a sample 57-bit DNA value for simulation
)
port map (
DOUT => DOUT, -- 1-bit output: DNA output data.
CLK => CLK, -- 1-bit input: Clock input.
DIN => DIN, -- 1-bit input: User data input pin.
READ => READ, -- 1-bit input: Active high load DNA, active low read input.
SHIFT => SHIFT -- 1-bit input: Active high shift enable input.
);
-- End of DNA_PORT_inst instantiation
Verilog Instantiation Template
// DNA_PORT: Device DNA Access Port
// 7 Series
// Xilinx HDL Language Template, version 2024.2
DNA_PORT #(
.SIM_DNA_VALUE(57'h000000000000000) // Specifies a sample 57-bit DNA value for simulation
)
DNA_PORT_inst (
.DOUT(DOUT), // 1-bit output: DNA output data.
.CLK(CLK), // 1-bit input: Clock input.
.DIN(DIN), // 1-bit input: User data input pin.
.READ(READ), // 1-bit input: Active high load DNA, active low read input.
.SHIFT(SHIFT) // 1-bit input: Active high shift enable input.
);
// End of DNA_PORT_inst instantiation
Related Information
- 7 Series FPGAs Configuration User Guide (UG470)