Primitive: 18Kb FIFO (First-In-First-Out) Block RAM Memory
Introduction
7 series devices contain several block RAM memories, each of which can be separately configured as a FIFO, an automatic error-correction RAM, or as a general-purpose 36 Kb or 18 Kb RAM/ROM memory. These Block RAM memories offer fast and flexible storage of large amounts of on-chip data. The FIFO18E1 uses the FIFO control logic and the 18 Kb Block RAM. This primitive can be used in a 4-bit wide by 4K deep, 9-bit wide by 2K deep, 18-bit wide by 1K deep, or a 36-bit wide by 512 deep configuration. The primitive can be configured in either synchronous or dual-clock (asynchronous) mode, with all associated FIFO flags and status signals.
When using the dual-clock mode with independent clocks, depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the clocks the simulation model only reflects the deassertion latency cycles listed in the User Guide.
Note:
For a 36-bit wide by 512 deep FIFO, the "FIFO18_36" mode must be
used. For deeper or wider configurations of the FIFO, the FIFO36E1
can be used. If error-correction circuitry is desired, the FIFO36E1
with "FIFO36_72" mode must be used.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| ALMOSTEMPTY | Output | 1 | Programmable flag to indicate the FIFO is almost empty. The ALMOST_EMPTY_OFFSET attribute specifies the threshold where this flag is triggered relative to full/empty. |
| ALMOSTFULL | Output | 1 | Programmable flag to indicate that the FIFO is almost full. The ALMOST_FULL_OFFSET attribute specifies the threshold where this flag is triggered relative to full/empty. |
| DI<31:0> | Input | 32 | FIFO data input bus. |
| DIP<3:0> | Input | 4 | FIFO parity data input bus. |
| DO<31:0> | Output | 32 | FIFO data output bus. |
| DOP<3:0> | Output | 4 | FIFO parity data output bus. |
| EMPTY | Output | 1 | Active-High logic to indicate that the FIFO is currently empty. |
| FULL | Output | 1 | Active-High logic indicates that the FIFO is full. |
| RDCLK | Input | 1 | Rising edge read clock. |
| RDCOUNT<11:0> | Output | 12 | Read count. |
| RDEN | Input | 1 | Active-High FIFO read enable. |
| RDERR | Output | 1 | Read error occurred. |
| REGCE | Input | 1 | Output register clock enable for pipelined synchronous FIFO. DO_REG must be set to 1 if using this enable. |
| RST | Input | 1 | Active-High (FIFO logic) asynchronous reset (for dual-clock FIFO), synchronous reset (for synchronous FIFO). Must be held for a minimum of 5 WRCLK/RDCLK cycles. |
| RSTREG | Input | 1 | Output register synchronous set/reset. DO_REG must be set to 1 if using this reset. |
| WRCLK | Input | 1 | Rising edge write clock. |
| WRCOUNT<11:0> | Output | 12 | Write count. |
| WREN | Input | 1 | Active-High FIFO write enable. |
| WRERR | Output | 1 | Write error occurred. When the FIFO is full, any additional write operation generates an error flag. Synchronous with WRCLK. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP Catalog | Yes |
| Macro support | Recommended |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| ALMOST_EMPTY _OFFSET | HEX | 13'h0000 to 13'h1fff | 13'h0080 | Specifies the amount of data contents in the RAM to trigger the ALMOST_EMPTY flag. |
| ALMOST_FULL _OFFSET | HEX | 13'h0000 to 13'h1fff | 13'h0080 | Specifies the amount of data contents in the RAM to trigger the ALMOST_FULL flag. |
| DATA_WIDTH | DECIMAL | 4, 9, 18, 36 | 4 | Specifies the desired data width for the FIFO. Note: If set to 36, FIFO_MODE must be set to FIFO18_36.
|
| DO_REG | DECIMAL | 1, 0 | 1 | Data pipeline register for EN_SYN. |
| EN_SYN | BOOLEAN | FALSE, TRUE | FALSE | EN_SYN denotes whether the FIFO is operating in either dual-clock (two independent clocks) or synchronous (a single clock) mode. Dual-clock must use DO_REG=1. |
| FIFO_MODE | STRING | "FIFO18", "FIFO18_36" | "FIFO18" | Selects "FIFO18" or "FIFO18_36" mode. Note:
If set to "FIFO18_36", DATA_WIDTH must be set to 36.
|
| FIRST_WORD_FALL _THROUGH | BOOLEAN | FALSE, TRUE | FALSE | If TRUE, the first write to the FIFO will appear on DO without a first RDEN assertion. |
| INIT | HEX | 36 bit HEX | All zeros | Specifies the initial value on the DO output after configuration. |
| SIM_DEVICE | STRING | "7SERIES" | "7SERIES" | Must be set to "7SERIES" to exhibit proper simulation behavior under all conditions. |
| SRVAL | HEX | 36 bit HEX | All zeros | Specifies the output value of the FIFO upon assertion of the synchronous reset (RSTREG) signal. Only valid for DO_REG=1. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
-- 7 Series
-- Xilinx HDL Language Template, version 2024.2
FIFO18E1_inst : FIFO18E1
generic map (
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
DATA_WIDTH => 4, -- Sets data width to 4-36
DO_REG => 1, -- Enable output register (1-0) Must be 1 if EN_SYN = FALSE
EN_SYN => FALSE, -- Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
FIFO_MODE => "FIFO18", -- Sets mode to FIFO18 or FIFO18_36
FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to FALSE, TRUE
INIT => X"000000000", -- Initial values on output port
SIM_DEVICE => "7SERIES", -- Must be set to "7SERIES" for simulation behavior
SRVAL => X"000000000" -- Set/Reset value for output port
)
port map (
-- Read Data: 32-bit (each) output: Read output data
DO => DO, -- 32-bit output: Data output
DOP => DOP, -- 4-bit output: Parity data output
-- Status: 1-bit (each) output: Flags and other FIFO status outputs
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output: Almost empty flag
ALMOSTFULL => ALMOSTFULL, -- 1-bit output: Almost full flag
EMPTY => EMPTY, -- 1-bit output: Empty flag
FULL => FULL, -- 1-bit output: Full flag
RDCOUNT => RDCOUNT, -- 12-bit output: Read count
RDERR => RDERR, -- 1-bit output: Read error
WRCOUNT => WRCOUNT, -- 12-bit output: Write count
WRERR => WRERR, -- 1-bit output: Write error
-- Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
RDCLK => RDCLK, -- 1-bit input: Read clock
RDEN => RDEN, -- 1-bit input: Read enable
REGCE => REGCE, -- 1-bit input: Clock enable
RST => RST, -- 1-bit input: Asynchronous Reset
RSTREG => RSTREG, -- 1-bit input: Output register set/reset
-- Write Control Signals: 1-bit (each) input: Write clock and enable input signals
WRCLK => WRCLK, -- 1-bit input: Write clock
WREN => WREN, -- 1-bit input: Write enable
-- Write Data: 32-bit (each) input: Write input data
DI => DI, -- 32-bit input: Data input
DIP => DIP -- 4-bit input: Parity input
);
-- End of FIFO18E1_inst instantiation
Verilog Instantiation Template
// FIFO18E1: 18Kb FIFO (First-In-First-Out) Block RAM Memory
// 7 Series
// Xilinx HDL Language Template, version 2024.2
FIFO18E1 #(
.ALMOST_EMPTY_OFFSET(13'h0080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(13'h0080), // Sets almost full threshold
.DATA_WIDTH(4), // Sets data width to 4-36
.DO_REG(1), // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
.EN_SYN("FALSE"), // Specifies FIFO as dual-clock (FALSE) or Synchronous (TRUE)
.FIFO_MODE("FIFO18"), // Sets mode to FIFO18 or FIFO18_36
.FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
.INIT(36'h000000000), // Initial values on output port
.SIM_DEVICE("7SERIES"), // Must be set to "7SERIES" for simulation behavior
.SRVAL(36'h000000000) // Set/Reset value for output port
)
FIFO18E1_inst (
// Read Data: 32-bit (each) output: Read output data
.DO(DO), // 32-bit output: Data output
.DOP(DOP), // 4-bit output: Parity data output
// Status: 1-bit (each) output: Flags and other FIFO status outputs
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
.ALMOSTFULL(ALMOSTFULL), // 1-bit output: Almost full flag
.EMPTY(EMPTY), // 1-bit output: Empty flag
.FULL(FULL), // 1-bit output: Full flag
.RDCOUNT(RDCOUNT), // 12-bit output: Read count
.RDERR(RDERR), // 1-bit output: Read error
.WRCOUNT(WRCOUNT), // 12-bit output: Write count
.WRERR(WRERR), // 1-bit output: Write error
// Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
.RDCLK(RDCLK), // 1-bit input: Read clock
.RDEN(RDEN), // 1-bit input: Read enable
.REGCE(REGCE), // 1-bit input: Clock enable
.RST(RST), // 1-bit input: Asynchronous Reset
.RSTREG(RSTREG), // 1-bit input: Output register set/reset
// Write Control Signals: 1-bit (each) input: Write clock and enable input signals
.WRCLK(WRCLK), // 1-bit input: Write clock
.WREN(WREN), // 1-bit input: Write enable
// Write Data: 32-bit (each) input: Write input data
.DI(DI), // 32-bit input: Data input
.DIP(DIP) // 4-bit input: Parity input
);
// End of FIFO18E1_inst instantiation