IBUFDS_DIFF_OUT_IBUFDISABLE - 2024.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2024-05-30
Version
2024.1 English

Primitive: Input Differential Buffer with Input Disable and Differential Output

Introduction

This design element is a differential input buffer used to connect internal logic to an external bidirectional pin. This element includes an input path disable as an additional power saving feature when the input is idle for a sustained time. The IOBUFDS_DIFF_OUT_IBUFDISABLE differs from the IOBUFDS_IBUFDISABLE in that it allows internal access to both phases of the differential signal.

Port Descriptions

Port Direction Width Function
I Input 1 Input p-side port connection. Connect directly to top-level port in the design.
IB Input 1 Input n-side port connection. Connect directly to top-level port in the design.
IBUFDISABLE Input 1 Disables input path through the buffer and forces to a logic high when USE_IBUFDISABLE is set to "TRUE" and this signal is asserted high. If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is idle for a period of time.
O Output 1 Buffer p-side output representing the input path to the device.
OB Output 1 Buffer n-side output representing the input path to the device.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DIFF_TERM STRING "TRUE", "FALSE" "FALSE" Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR STRING "TRUE", "FALSE" "TRUE" Allows a trade off of lower power consumption vs. highest performance when referenced I/O standards are used.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
USE_IBUFDISABLE STRING "TRUE", "FALSE" "TRUE" Enables or disables the feature of IBUFDISABLE.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer with Differential Output w/ Disable
--                              7 Series
-- Xilinx HDL Language Template, version 2024.1

IBUFDS_DIFF_OUT_IBUFDISABLE_inst : IBUFDS_DIFF_OUT_IBUFDISABLE
generic map (
   DIFF_TERM => "FALSE", -- Differential Termination
   IBUF_LOW_PWR => "TRUE", -- Low power "TRUE" vs. performance "FALSE" setting for referenced I/O standards
   IOSTANDARD => "DEFAULT", -- Specify the input I/O standard
   USE_IBUFDISABLE => "TRUE") -- Set to "TRUE" to enable IBUFDISABLE feature
port map (
   O => O,     -- Buffer diff_p output
   OB => OB,   -- Buffer diff_n output
   I => I,  -- Diff_p buffer input (connect directly to top-level port)
   IB => IB, -- Diff_n buffer input (connect directly to top-level port)
   IBUFDISABLE => IBUFDISABLE -- Buffer disable input, low=disable
);

-- End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation

Verilog Instantiation Template


// IBUFDS_DIFF_OUT_IBUFDISABLE: Differential Input Buffer with Differential Output with Input Disable
//                              7 Series
// Xilinx HDL Language Template, version 2024.1

IBUFDS_DIFF_OUT_IBUFDISABLE #(
   .DIFF_TERM("FALSE"),     // Differential Termination, "TRUE"/"FALSE"
   .IBUF_LOW_PWR("TRUE"),   // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT"),  // Specify the input I/O standard
   .USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IBUFDS_DIFF_OUT_IBUFDISABLE_inst (
   .O(O),   // Buffer diff_p output
   .OB(OB), // Buffer diff_n output
   .I(I),   // Diff_p buffer input (connect directly to top-level port)
   .IB(IB), // Diff_n buffer input (connect directly to top-level port)
   .IBUFDISABLE(IBUFDISABLE)  // Buffer disable input, high=disable
);

// End of IBUFDS_DIFF_OUT_IBUFDISABLE_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)