OUT_FIFO - 2024.1 English

Primitive: Output First-In, First-Out (FIFO) Buffer

The Output FIFO is a new resource located next to the I/O. This dedicated hardware is designed to help transition the data from fabric to the I/O, ODDR or OSERDESE2. It has two basic modes the first is a 4x4 mode where the data coming into the FIFO goes out at the same rate. The second mode is a 8x4 mode where the data coming out is serialized by a factor of 2. In other words, in 8x4 mode 8-bits go to the OUT_FIFO and 4-bits come out.

The Output FIFO is a new resource located next to the I/O. This dedicated hardware is designed to help transition the data from fabric to the I/O, ODDR or OSERDESE2. It has two basic modes the first is a 4x4 mode where the data coming into the FIFO goes out at the same rate. The second mode is a 8x4 mode where the data coming out is serialized by a factor of 2. In other words in 8x4 mode, 8-bits go to the OUT_FIFO and 4-bits come out. Features of this component include:

Array dimensions: 80 wide, 8 deep (8x4 mode); 40 wide, 8 deep (4x4 mode)
Empty and Full flags
Programmable Almost Empty and Almost Full flags

Port Descriptions

Port	Type	Width	Function
ALMOSTEMPTY	Output	1	Active-High output flag indicating the FIFO is almost empty. The threshold of the almost empty flag is set by the ALMOST_EMPTY_VALUE attribute.
ALMOSTFULL	Output	1	Active-High output flag indicating the FIFO is almost full. The threshold of the almost empty flag is set by the ALMOST_FULL_VALUE attribute.
D0<7:0>	Input	8	Channel 0 input bus.
D1<7:0>	Input	8	Channel 1 input bus.
D2<7:0>	Input	8	Channel 2 input bus.
D3<7:0>	Input	8	Channel 3 input bus.
D4<7:0>	Input	8	Channel 4 input bus.
D5<7:0>	Input	8	Channel 5 input bus.
D6<7:0>	Input	8	Channel 6 input bus.
D7<7:0>	Input	8	Channel 7 input bus.
D8<7:0>	Input	8	Channel 8 input bus.
D9<7:0>	Input	8	Channel 9 input bus.
EMPTY	Output	1	Active-High output flag indicating the FIFO is empty.
FULL	Output	1	Active-High output flag indicating the FIFO is full.
Q0<3:0>	Output	4	Channel 0 output bus.
Q1<3:0>	Output	4	Channel 1 output bus.
Q2<3:0>	Output	4	Channel 2 output bus.
Q3<3:0>	Output	4	Channel 3 output bus.
Q4<3:0>	Output	4	Channel 4 output bus.
Q5<7:0>	Output	8	Channel 5 output bus.
Q6<7:0>	Output	8	Channel 6 output bus.
Q7<3:0>	Output	4	Channel 7 output bus.
Q8<3:0>	Output	4	Channel 8 output bus.
Q9<3:0>	Output	4	Channel 9 output bus.
RDCLK	Input	1	Read clock.
RDEN	Input	1	Active-High read enable.
RESET	Input	1	Active-High asynchronous reset.
WRCLK	Input	1	Write clock.
WREN	Input	1	Active-High write enable.

Design Entry Method

Instantiation	Yes
Inference	No
IP Catalog	Yes
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
ALMOST_EMPTY _VALUE	DECIMAL	1, 2	1	Specifies the number of entries left before asserting the ALMOSTEMPTY output signal.
ALMOST_FULL _VALUE	DECIMAL	1, 2	1	Specifies the number of entries left before asserting the ALMOSTFULL output signal.
ARRAY_MODE	STRING	"ARRAY_MODE_8_X_4", "ARRAY_MODE_4_X_4"	"ARRAY_MODE _8_X_4"	Specifies serializer mode: "ARRAY_MODE_4_X_4": Four bits in, four bits out "ARRAY_MODE_4_X_8": Four bits in, eight bits out
OUTPUT _DISABLE	STRING	"FALSE", "TRUE"	"FALSE"	Disable output.
SYNCHRONOUS _MODE	STRING	"FALSE"	"FALSE"	Must always be set to false.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
--           7 Series
-- Xilinx HDL Language Template, version 2024.1

OUT_FIFO_inst : OUT_FIFO
generic map (
   ALMOST_EMPTY_VALUE => 1,          -- Almost empty offset (1-2)
   ALMOST_FULL_VALUE => 1,           -- Almost full offset (1-2)
   ARRAY_MODE => "ARRAY_MODE_8_X_4", -- ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
   OUTPUT_DISABLE => "FALSE",        -- Disable output (FALSE, TRUE)
   SYNCHRONOUS_MODE => "FALSE"       -- Must always be set to false.
)
port map (
   -- FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
   ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output: Almost empty flag
   ALMOSTFULL => ALMOSTFULL,   -- 1-bit output: Almost full flag
   EMPTY => EMPTY,             -- 1-bit output: Empty flag
   FULL => FULL,               -- 1-bit output: Full flag
   -- Q0-Q9: 4-bit (each) output: FIFO Outputs
   Q0 => Q0,                   -- 4-bit output: Channel 0 output bus
   Q1 => Q1,                   -- 4-bit output: Channel 1 output bus
   Q2 => Q2,                   -- 4-bit output: Channel 2 output bus
   Q3 => Q3,                   -- 4-bit output: Channel 3 output bus
   Q4 => Q4,                   -- 4-bit output: Channel 4 output bus
   Q5 => Q5,                   -- 8-bit output: Channel 5 output bus
   Q6 => Q6,                   -- 8-bit output: Channel 6 output bus
   Q7 => Q7,                   -- 4-bit output: Channel 7 output bus
   Q8 => Q8,                   -- 4-bit output: Channel 8 output bus
   Q9 => Q9,                   -- 4-bit output: Channel 9 output bus
   -- D0-D9: 8-bit (each) input: FIFO inputs
   D0 => D0,                   -- 8-bit input: Channel 0 input bus
   D1 => D1,                   -- 8-bit input: Channel 1 input bus
   D2 => D2,                   -- 8-bit input: Channel 2 input bus
   D3 => D3,                   -- 8-bit input: Channel 3 input bus
   D4 => D4,                   -- 8-bit input: Channel 4 input bus
   D5 => D5,                   -- 8-bit input: Channel 5 input bus
   D6 => D6,                   -- 8-bit input: Channel 6 input bus
   D7 => D7,                   -- 8-bit input: Channel 7 input bus
   D8 => D8,                   -- 8-bit input: Channel 8 input bus
   D9 => D9,                   -- 8-bit input: Channel 9 input bus
   -- FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
   RDCLK => RDCLK,             -- 1-bit input: Read clock
   RDEN => RDEN,               -- 1-bit input: Read enable
   RESET => RESET,             -- 1-bit input: Active high reset
   WRCLK => WRCLK,             -- 1-bit input: Write clock
   WREN => WREN                -- 1-bit input: Write enable
);

-- End of OUT_FIFO_inst instantiation

Verilog Instantiation Template


// OUT_FIFO: Output First-In, First-Out (FIFO) Buffer
//           7 Series
// Xilinx HDL Language Template, version 2024.1

OUT_FIFO #(
   .ALMOST_EMPTY_VALUE(1),          // Almost empty offset (1-2)
   .ALMOST_FULL_VALUE(1),           // Almost full offset (1-2)
   .ARRAY_MODE("ARRAY_MODE_8_X_4"), // ARRAY_MODE_8_X_4, ARRAY_MODE_4_X_4
   .OUTPUT_DISABLE("FALSE"),        // Disable output (FALSE, TRUE)
   .SYNCHRONOUS_MODE("FALSE")       // Must always be set to false.
)
OUT_FIFO_inst (
   // FIFO Status Flags: 1-bit (each) output: Flags and other FIFO status outputs
   .ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output: Almost empty flag
   .ALMOSTFULL(ALMOSTFULL),   // 1-bit output: Almost full flag
   .EMPTY(EMPTY),             // 1-bit output: Empty flag
   .FULL(FULL),               // 1-bit output: Full flag
   // Q0-Q9: 4-bit (each) output: FIFO Outputs
   .Q0(Q0),                   // 4-bit output: Channel 0 output bus
   .Q1(Q1),                   // 4-bit output: Channel 1 output bus
   .Q2(Q2),                   // 4-bit output: Channel 2 output bus
   .Q3(Q3),                   // 4-bit output: Channel 3 output bus
   .Q4(Q4),                   // 4-bit output: Channel 4 output bus
   .Q5(Q5),                   // 8-bit output: Channel 5 output bus
   .Q6(Q6),                   // 8-bit output: Channel 6 output bus
   .Q7(Q7),                   // 4-bit output: Channel 7 output bus
   .Q8(Q8),                   // 4-bit output: Channel 8 output bus
   .Q9(Q9),                   // 4-bit output: Channel 9 output bus
   // D0-D9: 8-bit (each) input: FIFO inputs
   .D0(D0),                   // 8-bit input: Channel 0 input bus
   .D1(D1),                   // 8-bit input: Channel 1 input bus
   .D2(D2),                   // 8-bit input: Channel 2 input bus
   .D3(D3),                   // 8-bit input: Channel 3 input bus
   .D4(D4),                   // 8-bit input: Channel 4 input bus
   .D5(D5),                   // 8-bit input: Channel 5 input bus
   .D6(D6),                   // 8-bit input: Channel 6 input bus
   .D7(D7),                   // 8-bit input: Channel 7 input bus
   .D8(D8),                   // 8-bit input: Channel 8 input bus
   .D9(D9),                   // 8-bit input: Channel 9 input bus
   // FIFO Control Signals: 1-bit (each) input: Clocks, Resets and Enables
   .RDCLK(RDCLK),             // 1-bit input: Read clock
   .RDEN(RDEN),               // 1-bit input: Read enable
   .RESET(RESET),             // 1-bit input: Active high reset
   .WRCLK(WRCLK),             // 1-bit input: Write clock
   .WREN(WREN)                // 1-bit input: Write enable
);

// End of OUT_FIFO_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)