BUFGMUX_CTRL - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: 2-to-1 Global Clock MUX Buffer

Introduction

This design element is a global clock buffer with two clock inputs, one clock output, and a select line used to cleanly select between one of two clocks driving the global clocking resource. This component is based on BUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the 2-to-1 MUX. S can switch anytime without causing a glitch on the output clock of the buffer.

Port Descriptions

Port Direction Width Function
I0 Input 1 Clock buffer input. This input is reflected on the output O when the S input is zero.
I1 Input 1 Clock buffer input. This input is reflected on the output O when the S input is one.
O Output 1 Clock buffer output.
S Input 1 Clock buffer select input. When low, selects I0 input and when high, the I1 input is selected.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
--               7 Series
-- Xilinx HDL Language Template, version 2023.2

BUFGMUX_CTRL_inst : BUFGMUX_CTRL
port map (
   O => O,   -- 1-bit output: Clock output
   I0 => I0, -- 1-bit input: Clock input (S=0)
   I1 => I1, -- 1-bit input: Clock input (S=1)
   S => S    -- 1-bit input: Clock select
);

-- End of BUFGMUX_CTRL_inst instantiation

Verilog Instantiation Template


// BUFGMUX_CTRL: 2-to-1 Global Clock MUX Buffer
//               7 Series
// Xilinx HDL Language Template, version 2023.2

BUFGMUX_CTRL BUFGMUX_CTRL_inst (
   .O(O),   // 1-bit output: Clock output
   .I0(I0), // 1-bit input: Clock input (S=0)
   .I1(I1), // 1-bit input: Clock input (S=1)
   .S(S)    // 1-bit input: Clock select
);

// End of BUFGMUX_CTRL_inst instantiation

Related Information

  • 7 Series FPGAs Clocking Resources User Guide (UG472)