DCIRESET - 2024.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2024-05-30
Version
2024.1 English

Primitive: Digitally Controlled Impedance Reset Component

Introduction

This design element is used to reset the Digitally Controlled Impedance (DCI) state machine after configuration has been completed. By toggling the RST input to the DCIRESET primitive while the device is operating, the DCI state-machine is reset and both phases of impedance adjustment proceed in succession. All I/Os using DCI will be unavailable until the LOCKED output from the DCIRESET block is asserted.

Port Descriptions

Port Direction Width Function
LOCKED Output 1 DCI state-machine LOCK status output. When low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable. Upon a low-to-high assertion, DCI I/Os are available for use.
RST Input 1 Active-High asynchronous reset input to DCI state-machine. After RST is asserted, I/Os using DCI will be unavailable until LOCKED is asserted.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- DCIRESET: Digitally Controlled Impedance Reset Component
--           7 Series
-- Xilinx HDL Language Template, version 2024.1

DCIRESET_inst : DCIRESET
port map (
   LOCKED => LOCKED, -- 1-bit output: LOCK status output
   RST => RST        -- 1-bit input: Active-high asynchronous reset input
);

-- End of DCIRESET_inst instantiation

Verilog Instantiation Template


// DCIRESET: Digitally Controlled Impedance Reset Component
//           7 Series
// Xilinx HDL Language Template, version 2024.1

DCIRESET DCIRESET_inst (
   .LOCKED(LOCKED), // 1-bit output: LOCK status output
   .RST(RST)        // 1-bit input: Active-high asynchronous reset input
);

// End of DCIRESET_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)