Primitive: Internal Configuration Access Port
Introduction
This design element gives you access to the configuration functions of the FPGA from the FPGA fabric. Using this component, commands and data can be written to and read from the configuration logic of the FPGA array. Because the improper use of this function can have a negative effect on the functionality and reliability of the FPGA, you should not use this element unless you are very familiar with its capabilities.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CLK | Input | 1 | Clock Input. |
| CSIB | Input | 1 | Active-Low ICAP Enable. |
| I<31:0> | Input | 32 | Configuration data input bus. |
| O<31:0> | Output | 32 | Configuration data output bus. |
| RDWRB | Input | 1 | Read/Write Select input. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP Catalog | No |
| Macro support | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| DEVICE_ID | HEX | 32'h03651093, 32'h036A2093, 32'h036A4093, 32'h036A6093, 32'h036BF093, 32'h036B1093, 32'h036B3093, 32'h036C2093, 32'h036C4093, 32'h036C6093, 32'h036DF093, 32'h036D1093, 32'h036D3093, 32'h036D5093, 32'h036D9093, 32'h0362C093, 32'h0362D093, 32'h0363B093, 32'h0364C093, 32'h0371F093, 32'h0372C093, 32'h0377F093, 32'h03627093, 32'h03628093, 32'h03631093, 32'h03636093, 32'h03642093, 32'h03647093, 32'h03656093, 32'h03667093, 32'h03671093, 32'h03676093, 32'h03680093, 32'h03681093, 32'h03682093, 32'h03687093, 32'h03691093, 32'h03692093, 32'h03696093, 32'h03702093, 32'h03704093, 32'h03711093, 32'h03722093, 32'h03727093, 32'h03731093, 32'h03747093, 32'h03751093, 32'h03752093, 32'h03762093, 32'h03771093, 32'h03782093 | 0'h3651093 | Specifies the pre-programmed Device ID value to be used for simulation purposes. |
| ICAP_WIDTH | STRING | "X32", "X8", "X16" | "X32" | Specifies the input and output data width. |
| SIM_CFG_FILE _NAME | STRING | String representing file name and location | "NONE" | Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ICAPE2: Internal Configuration Access Port
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
ICAPE2_inst : ICAPE2
generic map (
DEVICE_ID => X"3651093", -- Specifies the pre-programmed Device ID value to be used for simulation
-- purposes.
ICAP_WIDTH => "X32", -- Specifies the input and output data width.
SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
-- model.
)
port map (
O => O, -- 32-bit output: Configuration data output bus
CLK => CLK, -- 1-bit input: Clock Input
CSIB => CSIB, -- 1-bit input: Active-Low ICAP Enable
I => I, -- 32-bit input: Configuration data input bus
RDWRB => RDWRB -- 1-bit input: Read/Write Select input
);
-- End of ICAPE2_inst instantiation
Verilog Instantiation Template
// ICAPE2: Internal Configuration Access Port
// 7 Series
// Xilinx HDL Language Template, version 2024.1
ICAPE2 #(
.DEVICE_ID(32'h3651093), // Specifies the pre-programmed Device ID value to be used for simulation
// purposes.
.ICAP_WIDTH("X32"), // Specifies the input and output data width.
.SIM_CFG_FILE_NAME("NONE") // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
// model.
)
ICAPE2_inst (
.O(O), // 32-bit output: Configuration data output bus
.CLK(CLK), // 1-bit input: Clock Input
.CSIB(CSIB), // 1-bit input: Active-Low ICAP Enable
.I(I), // 32-bit input: Configuration data input bus
.RDWRB(RDWRB) // 1-bit input: Read/Write Select input
);
// End of ICAPE2_inst instantiation
Related Information
- 7 Series FPGAs Configuration User Guide (UG470)