Primitive: Register Capture
Introduction
This element provides
user control and synchronization over when and how the capture register
(flip-flop and latch) information task is requested. The readback
function is provided through dedicated configuration port instructions.
However, without this element, the readback data is synchronized to
the configuration clock. Only register (flip-flop and latch) states
can be captured. Although LUT RAM, SRL, and block RAM states are readback,
they cannot be captured. An asserted high CAP signal indicates that
the registers in the device are to be captured at the next Low-to-High
clock transition. By default, data is captured after every trigger
when transition on CLK while CAP is asserted. To limit the readback
operation to a single data capture, add the ONESHOT=TRUE attribute
to this element.
Port Descriptions
| Port |
Direction |
Width |
Function |
| CAP |
Input |
1 |
Capture Input |
| CLK |
Input |
1 |
Clock Input |
Design Entry Method
| Instantiation |
Recommended |
| Inference |
No |
| IP Catalog |
No |
| Macro support |
No |
Available Attributes
| Attribute |
Type |
Allowed Values |
Default |
Description |
| ONESHOT |
STRING |
"TRUE", "FALSE" |
"TRUE" |
Specifies the procedure for performing single readback per
CAP trigger. |
VHDL
Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CAPTUREE2: Register Capture
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
CAPTUREE2_inst : CAPTUREE2
generic map (
ONESHOT => "TRUE" -- Specifies the procedure for performing single readback per CAP trigger.
)
port map (
CAP => CAP, -- 1-bit input: Capture Input
CLK => CLK -- 1-bit input: Clock Input
);
-- End of CAPTUREE2_inst instantiation
Verilog
Instantiation Template
// CAPTUREE2: Register Capture
// 7 Series
// Xilinx HDL Language Template, version 2024.1
CAPTUREE2 #(
.ONESHOT("TRUE") // Specifies the procedure for performing single readback per CAP trigger.
)
CAPTUREE2_inst (
.CAP(CAP), // 1-bit input: Capture Input
.CLK(CLK) // 1-bit input: Clock Input
);
// End of CAPTUREE2_inst instantiation
