Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
Introduction
This design element is a transparent data latch with asynchronous preset and gate enable. When the asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflects the data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.
This latch is asynchronously preset, output High, when power is applied. Power-on conditions are simulated when global set/reset (GSR) is active.
Logic Table
Inputs | Outputs | |||
---|---|---|---|---|
PRE | GE | G | D | Q |
1 | X | X | X | 1 |
0 | 0 | X | X | No Change |
0 | 1 | 1 | D | D |
0 | 1 | 0 | X | No Change |
0 | 1 | ↓ | D | D |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | BINARY | 0, 1 | 1 | Specifies the initial value upon power-up or the assertion of GSR for the (Q) port. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LDPE: Transparent latch with Asynchronous Set and
-- Gate Enable.
-- 7 Series
-- Xilinx HDL Language Template, version 2024.2
LDPE_inst : LDPE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => Q, -- Data output
CLR => CLR, -- Asynchronous preset/set input
D => D, -- Data input
G => G, -- Gate input
GE => GE -- Gate enable input
);
-- End of LDPE_inst instantiation
Verilog Instantiation Template
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
// 7 Series
// Xilinx HDL Language Template, version 2024.2
LDPE #(
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
) LDPE_inst (
.Q(Q), // Data output
.PRE(PRE), // Asynchronous preset/set input
.D(D), // Data input
.G(G), // Gate input
.GE(GE) // Gate enable input
);
// End of LDPE_inst instantiation
Related Information
- 7 Series FPGAs Configurable Logic Block User Guide (UG474)