STARTUPE2 - 2024.1 English

Primitive: STARTUP Block

Introduction

This design element is used to interface device pins and logic to the global asynchronous set/reset (GSR) signal, the global 3-state (GTS) dedicated routing or the internal configuration signals or a few of the dedicated configuration pins.

Port Descriptions

Port	Direction	Width	Function
CFGCLK	Output	1	Configuration main clock output.
CFGMCLK	Output	1	Configuration internal oscillator clock output.
CLK	Input	1	User start-up clock input. For Spartan-7 7S6 and 7S15 devices, the user-defined CCLK (UserClk value for the BITSTREAM.STARTUP.STARTUPCLK property) for the start-up sequence is not supported.
EOS	Output	1	Active-High output signal indicating the End Of Startup.
GSR	Input	1	Global Set/Reset input (GSR cannot be used for the port name).
GTS	Input	1	Global 3-state input (GTS cannot be used for the port name).
KEYCLEARB	Input	1	Clear AES Decrypter Key input from battery-backed RAM (BBRAM).
PACK	Input	1	PROGRAM acknowledge input.
PREQ	Output	1	PROGRAM request to fabric output.
USRCCLKO	Input	1	User CCLK input. For Zynq-7000 devices, this input must be tied to GND.
USRCCLKTS	Input	1	User CCLK 3-state enable input. For Zynq-7000 devices, this input must be tied to VCC.
USRDONEO	Input	1	User DONE pin output control.
USRDONETS	Input	1	User DONE 3-state enable output.

Design Entry Method

Instantiation	Recommended
Inference	No
IP Catalog	No
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
PROG_USR	STRING	"FALSE", "TRUE"	"FALSE"	Activate program event security feature. Requires encrypted bitstreams.
SIM_CCLK_FREQ	FLOAT (nS)	0.0 to 10.0	0.0	Set the Configuration Clock Frequency (ns) for simulation.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- STARTUPE2: STARTUP Block
--            7 Series
-- Xilinx HDL Language Template, version 2024.1

STARTUPE2_inst : STARTUPE2
generic map (
   PROG_USR => "FALSE",  -- Activate program event security feature. Requires encrypted bitstreams.
   SIM_CCLK_FREQ => 0.0  -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map (
   CFGCLK => CFGCLK,       -- 1-bit output: Configuration main clock output
   CFGMCLK => CFGMCLK,     -- 1-bit output: Configuration internal oscillator clock output
   EOS => EOS,             -- 1-bit output: Active high output signal indicating the End Of Startup.
   PREQ => PREQ,           -- 1-bit output: PROGRAM request to fabric output
   CLK => CLK,             -- 1-bit input: User start-up clock input
   GSR => GSR,             -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
   GTS => GTS,             -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
   KEYCLEARB => KEYCLEARB, -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
   PACK => PACK,           -- 1-bit input: PROGRAM acknowledge input
   USRCCLKO => USRCCLKO,   -- 1-bit input: User CCLK input
                           -- For Zynq-7000 devices, this input must be tied to GND
   USRCCLKTS => USRCCLKTS, -- 1-bit input: User CCLK 3-state enable input
                           -- For Zynq-7000 devices, this input must be tied to VCC
   USRDONEO => USRDONEO,   -- 1-bit input: User DONE pin output control
   USRDONETS => USRDONETS  -- 1-bit input: User DONE 3-state enable output
);

-- End of STARTUPE2_inst instantiation

Verilog Instantiation Template


// STARTUPE2: STARTUP Block
//            7 Series
// Xilinx HDL Language Template, version 2024.1

STARTUPE2 #(
   .PROG_USR("FALSE"),  // Activate program event security feature. Requires encrypted bitstreams.
   .SIM_CCLK_FREQ(0.0)  // Set the Configuration Clock Frequency(ns) for simulation.
)
STARTUPE2_inst (
   .CFGCLK(CFGCLK),       // 1-bit output: Configuration main clock output
   .CFGMCLK(CFGMCLK),     // 1-bit output: Configuration internal oscillator clock output
   .EOS(EOS),             // 1-bit output: Active high output signal indicating the End Of Startup.
   .PREQ(PREQ),           // 1-bit output: PROGRAM request to fabric output
   .CLK(CLK),             // 1-bit input: User start-up clock input
   .GSR(GSR),             // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
   .GTS(GTS),             // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
   .KEYCLEARB(KEYCLEARB), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
   .PACK(PACK),           // 1-bit input: PROGRAM acknowledge input
   .USRCCLKO(USRCCLKO),   // 1-bit input: User CCLK input
                          // For Zynq-7000 devices, this input must be tied to GND
   .USRCCLKTS(USRCCLKTS), // 1-bit input: User CCLK 3-state enable input
                          // For Zynq-7000 devices, this input must be tied to VCC
   .USRDONEO(USRDONEO),   // 1-bit input: User DONE pin output control
   .USRDONETS(USRDONETS)  // 1-bit input: User DONE 3-state enable output
);

// End of STARTUPE2_inst instantiation

Related Information

7 Series FPGAs Configuration User Guide (UG470)