Primitive: Output Buffer
Introduction
This design element is a simple output buffer used to drive output signals to the FPGA device pins that do not need to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected to every output port in the design.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists in input/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard used by this element is LVCMOS18. Also, this element has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
O | Output | 1 | Output of OBUF to be connected directly to top-level output port. |
I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DRIVE | INTEGER | 2, 4, 6, 8, 12, 16, 24 | 12 | Specifies the output current drive strength of the I/O. It is suggested that you set this to the lowest setting tolerable for the design drive and timing requirements. |
IOSTANDARD | STRING | See Data Sheet | "DEFAULT" | Assigns an I/O standard to the element. |
SLEW | STRING | "SLOW" or "FAST" | "SLOW" | Specifies the slew rate of the output driver. Consult the product Data Sheet for recommendations of the best setting for this attribute. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUF: Single-ended Output Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
OBUF_inst : OBUF
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I -- Buffer input
);
-- End of OBUF_inst instantiation
Verilog Instantiation Template
// OBUF: Single-ended Output Buffer
// 7 Series
// Xilinx HDL Language Template, version 2024.1
OBUF #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUF_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I) // Buffer input
);
// End of OBUF_inst instantiation
Related Information
- 7 Series FPGAs SelectIO Resources User Guide (UG471)