IOBUFDS_DIFF_OUT_DCIEN - 2024.1 English

Primitive: Bi-Directional Differential Buffer with DCI Disable, Input Disable, and Differential Output

Introduction

This design element is a bidirectional differential I/O buffer used to connect internal logic to an external bidirectional pin. This element includes Digitally Controlled Impedance (DCI) termination enable/ disable as well as input path disable as additional power saving features when the I/O is in an unused state or being used as an output for a sustained period of time. The IOBUFDS_DIFF_OUT_DCIEN differs from the IOBUFDS_DCIEN in that it allows internal access to both phases of the differential signal. This element may only be placed in High Performance (HP) banks in the 7 series devices.

Port Descriptions

Port	Direction	Width	Function
IO	In/out	1	Bi-directional p-side port connection. Connect directly to top-level port in the design.
IOB	In/out	1	Bi-directional n-side port connection. Connect directly to top-level port in the design.
I	Input	1	Buffer input representing the output path to the device.
IBUFDISABLE	Input	1	Disables input path. When this signal is asserted HIGH and the attribute USE_IBUFDISABLE is set to "TRUE", the input path through the input buffer is disabled and forced to a logic HIGH. If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions
DCITERMDISABLE	Input	1	Disables DCI termination. When this signal is asserted HIGH, DCI termination is disabled. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions.
TM	Input	1	P-side or master side of the high impedance 3-state mode when the I/O is being used for a read (input) operation. The TM pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE".
TS	Input	1	N-side or slave side of the high impedance 3-state mode when the I/O is being used for a read (input) operation. The TM pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE".
O	Output	1	Buffer p-side output representing the input path to the device.
OB	Output	1	Buffer n-side output representing the input path to the device.

Design Entry Method

Instantiation	Yes
Inference	No
IP Catalog	Yes
Macro support	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DIFF_TERM	STRING	"TRUE", "FALSE"	"FALSE"	Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR	STRING	"TRUE", "FALSE"	"TRUE"	Allows a trade off of lower power consumption vs highest performance.
IOSTANDARD	STRING	See Data Sheet	"DEFAULT"	Assigns an I/O standard to the element.
USE_IBUFDISABLE	STRING	"TRUE", "FALSE"	"TRUE"	Enables or disables the feature of IBUFDISABLE. Set to FALSE when it is not desirable to have the T pin disable input path to allow a read during write operation. When set to TRUE deasserting T (IO used as output) or asserting IBUFDISABLE will disable the input path through the buffer and forces to a logic high.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- IOBUFDS_DIFF_OUT_DCIEN: Differential Bi-directional Buffer with Differential Output,
--                         Digital Controlled Impedance (DCI)and Input path enable/disable
--                         May only be placed in High Performance (HP) Banks
--                         7 Series
-- Xilinx HDL Language Template, version 2024.1

IOBUFDS_DIFF_OUT_DCIEN_inst : IOBUFDS_DIFF_OUT_DCIEN
generic map (
   DIFF_TERM => "FALSE", -- Differential Termination (TRUE/FALSE)
   IBUF_LOW_PWR => "TRUE", -- Low Power - TRUE, High Performance = FALSE
   IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
   USE_IBUFDISABLE => "TRUE") -- Use IBUFDISABLE function, "TRUE" or "FALSE"
port map (
   O => O,     -- Buffer p-side output
   OB => OB,   -- Buffer n-side output
   IO => IO,   -- Diff_p inout (connect directly to top-level port)
   IOB => IOB, -- Diff_n inout (connect directly to top-level port)
   DCITERMDISABLE => DCITERMDISABLE, -- DCI Termination enable input
   I => I,     -- Buffer input
   IBUFTERMDISABLE => IBUFTERMDISABLE, -- input disable input, low=disable
   TM => TM,   -- 3-state enable input, high=input, low=output
   TS => TS    -- 3-state enable input, high=output, low=input
);

-- End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation

Verilog Instantiation Template


// IOBUFDS_DIFF_OUT_DCIEN: Differential Bi-directional Buffer with Differential Output,
//                         Digital Controlled Impedance (DCI)and Input path enable/disable
//                         May only be placed in High Performance (HP) Banks
//                         7 Series
// Xilinx HDL Language Template, version 2024.1

IOBUFDS_DIFF_OUT_DCIEN #(
   .DIFF_TERM("FALSE"),     // Differential Termination ("TRUE"/"FALSE")
   .IBUF_LOW_PWR("TRUE"),   // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("BLVDS_25"), // Specify the I/O standard
   .USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
) IOBUFDS_DIFF_OUT_DCIEN_inst (
   .O(O),     // Buffer p-side output
   .OB(OB),   // Buffer n-side output
   .IO(IO),   // Diff_p inout (connect directly to top-level port)
   .IOB(IOB), // Diff_n inout (connect directly to top-level port)
   .DCITERMDISABLE(DCITERMDISABLE), //  DCI Termination enable input
   .I(I),                           // Buffer input
   .IBUFDISABLE(IBUFDISABLE),       // Input disable input, high=disable
   .TM(TM),   // 3-state enable input, high=input, low=output
   .TS(TS)    // 3-state enable input, high=input, low=output
);

// End of IOBUFDS_DIFF_OUT_DCIEN_inst instantiation

Related Information

7 Series FPGAs SelectIO Resources User Guide (UG471)