Macro: Dual Clock First-In, First-Out (FIFO) RAM Buffer
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36 Kb or 18 Kb RAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFO can be configured as an 18 Kb or 36 Kb memory. This unimacro configures the FIFO for using independent read and writes clocks. Data is read from the FIFO on the rising edge of the read clock and written to the FIFO on the rising edge of write clock.
Depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the clocks, the simulation model only reflects the deassertion latency cycles listed in the User Guide.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| ALMOSTEMPTY | Output | 1 | Almost all valid entries in FIFO have been read. |
| ALMOSTFULL | Output | 1 | Almost all entries in FIFO memory have been filled. |
| DO | Output | See Port Configuration table. | Data output bus addressed by ADDR. |
| EMPTY | Output | 1 | FIFO is empty. |
| FULL | Output | 1 | All entries in FIFO memory are filled. |
| RDCOUNT | Output | See Port Configuration table. | FIFO data read pointer. |
| RDERR | Output | 1 | When the FIFO is empty, any additional read operation generates an error flag. |
| WRCOUNT | Output | See Port Configuration table. | FIFO data write pointer. |
| WRERR | Output | 1 | When the FIFO is full, any additional write operation generates an error flag. |
| DI | Input | See Port Configuration table. | Data input bus addressed by ADDR. |
| RDCLK | Input | 1 | Clock for Read domain operation. |
| RDEN | Input | 1 | Read Enable. |
| RST | Input | 1 | Asynchronous reset. |
| WRCLK | Input | 1 | Clock for Write domain operation. |
| WREN | Input | 1 | Write Enable. |
Port Configuration
This unimacro
is a parameterizable version of the primitive, and can be instantiated
only. Use this table to correctly configure the unimacro to meet design
needs.
| DATA_WIDTH | FIFO_SIZE | WRCOUNT | RDCOUNT |
|---|---|---|---|
| 72 - 37 | 36 Kb | 9 | 9 |
| 36 - 19 | 36 Kb | 10 | 10 |
| 18 Kb | 9 | 9 | |
| 18 - 10 | 36 Kb | 11 | 11 |
| 18 Kb | 10 | 10 | |
| 9-5 | 36 Kb | 12 | 12 |
| 18 Kb | 11 | 11 | |
| 1-4 | 36 Kb | 13 | 13 |
| 18 Kb | 12 | 12 |
Design Entry Method
This unimacro is a parameterizable version of the primitive, and can be
instantiated only. Consult the Port Configuration section to correctly configure
this element to meet your design needs.
| Instantiation | Yes |
| Inference | No |
| IP Catalog | No |
| Macro support | Recommended |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| ALMOST_EMPTY_OFFSET | HEX | 13-Bit Value | All zeros | Setting determines the difference between EMPTY and ALMOSTEMPTY conditions. Must be set using hexadecimal notation. |
| ALMOST_FULL_OFFSET | HEX | 13-Bit Value | All zeros | Setting determines the difference between FULL and ALMOSTFULL conditions. Must be set using hexadecimal notation. |
| DATA_WIDTH | INTEGER | 1 - 72 | 4 | Width of DI/DO bus. |
| DEVICE | STRING | "7SERIES" | "7SERIES" | Target hardware architecture. |
| FIFO_SIZE | STRING | "18Kb", "36Kb" | "18Kb" | Configures the FIFO as 18 Kb or 36 Kb memory. |
| FIRST_WORD_FALL_THROUGH | BOOLEAN | FALSE, TRUE | FALSE | If TRUE, the first word written into the empty FIFO appears at the FIFO output without RDEN asserted. |
VHDL Instantiation Template
Unless
they already exist, copy the following four statements and paste them
before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
-- FIFO_DUALCLOCK_MACRO: Dual-Clock First-In, First-Out (FIFO) RAM Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2024.1
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
-----------------------------------------------------------------
-- DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width --
-- ===========|===========|============|=======================--
-- 37-72 | "36Kb" | 512 | 9-bit --
-- 19-36 | "36Kb" | 1024 | 10-bit --
-- 19-36 | "18Kb" | 512 | 9-bit --
-- 10-18 | "36Kb" | 2048 | 11-bit --
-- 10-18 | "18Kb" | 1024 | 10-bit --
-- 5-9 | "36Kb" | 4096 | 12-bit --
-- 5-9 | "18Kb" | 2048 | 11-bit --
-- 1-4 | "36Kb" | 8192 | 13-bit --
-- 1-4 | "18Kb" | 4096 | 12-bit --
-----------------------------------------------------------------
FIFO_DUALCLOCK_MACRO_inst : FIFO_DUALCLOCK_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
FIRST_WORD_FALL_THROUGH => FALSE) -- Sets the FIFO FWFT to TRUE or FALSE
port map (
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output almost empty
ALMOSTFULL => ALMOSTFULL, -- 1-bit output almost full
DO => DO, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => EMPTY, -- 1-bit output empty
FULL => FULL, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => RDERR, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => WRERR, -- 1-bit output write error
DI => DI, -- Input data, width defined by DATA_WIDTH parameter
RDCLK => RDCLK, -- 1-bit input read clock
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WRCLK => WRCLK, -- 1-bit input write clock
WREN => WREN -- 1-bit input write enable
);
-- End of FIFO_DUALCLOCK_MACRO_inst instantiation
Verilog Instantiation Template
// FIFO_DUALCLOCK_MACRO: Dual Clock First-In, First-Out (FIFO) RAM Buffer
// 7 Series
// Xilinx HDL Language Template, version 2024.1
/////////////////////////////////////////////////////////////////
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
// ===========|===========|============|=======================//
// 37-72 | "36Kb" | 512 | 9-bit //
// 19-36 | "36Kb" | 1024 | 10-bit //
// 19-36 | "18Kb" | 512 | 9-bit //
// 10-18 | "36Kb" | 2048 | 11-bit //
// 10-18 | "18Kb" | 1024 | 10-bit //
// 5-9 | "36Kb" | 4096 | 12-bit //
// 5-9 | "18Kb" | 2048 | 11-bit //
// 1-4 | "36Kb" | 8192 | 13-bit //
// 1-4 | "18Kb" | 4096 | 12-bit //
/////////////////////////////////////////////////////////////////
FIFO_DUALCLOCK_MACRO #(
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DEVICE("7SERIES"), // Target device: "7SERIES"
.FIFO_SIZE ("18Kb"), // Target BRAM: "18Kb" or "36Kb"
.FIRST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO_DUALCLOCK_MACRO_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
.EMPTY(EMPTY), // 1-bit output empty
.FULL(FULL), // 1-bit output full
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
.RDERR(RDERR), // 1-bit output read error
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
.WRERR(WRERR), // 1-bit output write error
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
.RDCLK(RDCLK), // 1-bit input read clock
.RDEN(RDEN), // 1-bit input read enable
.RST(RST), // 1-bit input reset
.WRCLK(WRCLK), // 1-bit input write clock
.WREN(WREN) // 1-bit input write enable
);
// End of FIFO_DUALCLOCK_MACRO_inst instantiation
Related Information
- 7 Series FPGAs Memory Resources User Guide (UG473)