place_design - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

The place_design command runs placement on the design. Like the other implementation commands, place_design is re-entrant in nature. For a partially placed design, the Vivado placer uses the existing placement as the starting point instead of starting from scratch.

place_design Syntax

place_design  [-directive <arg>] [-subdirective <args>] [-no_timing_driven]
              [-timing_summary] [-unplace] [-post_place_opt] [-no_psip]
              [-sll_align_opt] [-clock_vtree_type <arg>] [-no_bufg_opt]
              [-ultrathreads] [-no_noc_opt] [-quiet] [-verbose]

place_design Example Script

# Run placement, save results to checkpoint, report timing estimates
place_design
write_checkpoint -force $outputDir/post_place
report_timing_summary -file $outputDir/post_place_timing_summary.rpt

The place_design example script places the in-memory design. It then writes a design checkpoint after completing placement, generates a timing summary report, and writes the report to the specified file.

place_design -clock_vtree_type

The -clock_vtree_type option is used in place_design to specify the type of clock tree to be used. The valid values are balanced, intraSLR, and interSLR.

Use the -clock_vtree_type option to select the clock tree that minimizes the clock skew for the types of timing challenges seen in the design:

  • Select intraSLR to minimize clock skew within each SLR
  • Select interSLR to minimize clock skew on paths between SLRs
  • Select balanced for the best compromise between intraSLR and interSLR
Note: Placer clock v-tree type properties are case sensitive. Using the wrong case generates an error message stopping the placer flow.