The synth_design
command can be used in both Project Mode and
Non-Project Mode. It runs Vivado synthesis on RTL sources with
the specified options, and reads the design into memory after synthesis.
synth_design Syntax
synth_design [-name <arg>] [-part <arg>] [-constrset <arg>] [-top <arg>]
[-include_dirs <args>] [-generic <args>] [-verilog_define <args>]
[-flatten_hierarchy <arg>] [-gated_clock_conversion <arg>]
[-directive <arg>] [-rtl] [-bufg <arg>] [-no_lc]
[-shreg_min_size <arg>] [-mode <arg>] [-fsm_extraction <arg>]
[-rtl_skip_mlo] [-rtl_skip_ip] [-rtl_skip_constraints]
[-srl_style <arg>] [-keep_equivalent_registers]
[-resource_sharing <arg>] [-cascade_dsp <arg>]
[-control_set_opt_threshold <arg>] [-incremental <arg>]
[-max_bram <arg>] [-max_uram <arg>] [-max_dsp <arg>]
[-max_bram_cascade_height <arg>] [-max_uram_cascade_height <arg>]
[-retiming] [-no_srlextract] [-assert] [-no_timing_driven]
[-sfcu] [-debug_log] [-quiet] [-verbose]
synth_design Example Script
The following is an excerpt from the create_bft_batch.tcl script found in the examples/Vivado_Tutorials directory of the software installation.
# Setup design sources and constraints
read_vhdl -library bftLib [ glob ./Sources/hdl/bftLib/*.vhdl ]
read_vhdl ./Sources/hdl/bft.vhdl
read_verilog [ glob ./Sources/hdl/*.v ]
read_xdc ./Sources/bft_full.xdc
# Run synthesis, report utilization and timing estimates, write design checkpoint
synth_design -top bft -part xc7k70tfbg484-2 -flatten rebuilt
write_checkpoint -force $outputDir/post_synth
For more information on using the synth_design
example script, see the
Vivado
Design Suite Tutorial: Design Flows Overview (UG888) and the
Vivado
Design Suite User Guide: Synthesis (UG901).
The synth_design
example script reads VHDL and Verilog files, reads
a constraint file, and synthesizes the design on the specified part. The design is
opened by the Vivado tools into memory when
synth_design
completes. A design checkpoint is written after
completing synthesis.
For more information on the synth_design
Tcl
command, see
Vivado
Design Suite Tcl Command Reference Guide (UG835). This
reference guide also provides a complete description of the Tcl commands and their
options.