link_design - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

The link_design command creates an in-memory design from netlist sources (such as from a third-party synthesis tool), and links the netlists and design constraints with the target part.

Tip: The link_design command supports both Project Mode and Non-Project Mode to create the netlist design. Use link_design -part <arg> without a netlist loaded, to open a blank design for device exploration.

link_design Syntax

link_design	[-name <arg>] [-part <arg>] [-constrset <arg>] [-top <arg>]
					[-mode <arg>] [-pr_config <arg>] [-reconfig_partitions <args>] 
					[-partitions <args>] [-quiet] [-verbose]

link_design Example Script

# Open named design from netlist sources.
link_design -name netDriven -constrset constrs_1 -part xc7k325tfbg900-1

If you use link_design while a design is already in memory, the Vivado tools prompt you to save any changes to the current design before opening the new design.

Note: For more information on the Partial Reconfiguration options of link_design, see section Reading Design Modules in the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).

Immediately after opening the in-memory synthesized design, run report_timing_summary to check timing constraints. This ensures that the design goals are complete and reasonable. For more detailed descriptions of the report_timing_summary command, see Vivado Design Suite Tcl Command Reference Guide (UG835).