MBUFG Optimization - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

For Versal devices, a new Multi-Clock Buffer (MBUFG) provides divide by 1, 2, 4, 8 clocks of the clock input on its O1, O2, O3, O4 outputs. The MBUFG clock outputs are all routed on the same global clock routing resources and only divided once they reach the BUFDIV_LEAF route-thru Bels. MBUFG driven clocks consume less routing resources and clock skew is minimized for synchronous CDC paths between clocks driven by the same MBUFG because the common node is closer to the source and destination.

The MBUFG optimization transforms parallel clock buffers driven by a common driver or clock modifying block (CMB), such as MMCM, DPLL, or XPLL, to MBUFG. The transformation occurs if the divide factors of the parallel clocks are divide by 1, 2, 4, 8 of a common clock. For CMB driven clocks, the phase shift has to be 0 and the duty cycle 50%. If the clock nets driven by the BUFGs have conflicting constraints such as CLOCK_DELAY_GROUP or USER_CLOCK_ROOT the transformation is also prevented. The transformation is only occurring when it is safe to do so without corrupting timing constraints. The following transformations are supported:

  • Parallel BUFGCEs connected to a CMB to an MBUFGCE.
  • Parallel BUFGCE_DIVs connected to a common clock driver to an MBUFGCE.
  • Parallel BUFG_GTs connected to a common clock driver to an MBUFG_GT.

In addition to the global optimization using the -mbufg_opt option, you can control the conversion of selected BUFGs to MBUFG using the MBUFG_GROUP property. You must set the MBUFG_GROUP constraint on the net segment directly connected to the clock buffer. The following example shows the property applied to two clock nets, which are directly driven by the clock buffers:

set_property MBUFG_GROUP grp1 [get_nets -of [get_pins {BUFG_inst_0/O BUFG_inst_1/O}]

The picture in the following figure shows an MMCM driving several BUFGCE buffers. The CLKOUTn driven clocks are integer divides of 1, 2, 4, 8 of the CLKOUT1 driven clock. After the MBUFG optimization the four BUFGCEs are transformed to a single MBUFGCE and the CLKOUT1 driven clock is connected to the MBUFGCE I pin. The loads that were driven by the BUFGCEs are connected to the MBUFGCE O1, O2, O3, O4 pins.

Figure 1. MBUFG Optimization