Design Placement Optimization - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

The Vivado placer simultaneously optimizes the design placement for:

Timing slack
Placement of cells in timing-critical paths is chosen to minimize negative slack.
Wirelength
Overall placement is driven to minimize the overall wirelength of connections.
Congestion
The Vivado placer monitors pin density and spreads cells to reduce potential routing congestion.