| Implementation Strategy Name | Description |
|---|---|
| AMD Vivado™ Implementation Defaults | Balances runtime with trying to achieve timing closure. |
| Performance_Explore | Uses multiple algorithms for optimization, placement, and routing to get potentially better results. |
| Performance_ExplorePostRoutePhysOpt | Similar to Peformance_Explore but adds
phys_opt_design after routing for further
improvements. |
| Performance_ExploreWithRemap | Similar to Performance_Explore but with logic remapped to lower logic levels. |
| Performance_WLBlockPlacement | Ignore timing constraints for placing block RAM and DSPs, use wirelength instead. |
| Performance_WLBlockPlacementFanoutOpt | Ignore timing constraints for placing block RAM and DSPs, use wirelength instead, and perform aggressive replication of high fanout drivers. |
| Performance_EarlyBlockPlaceent | Finalize placement of Block RAM and DSPs in the early stages of global placement. |
| Performance_NetDelay_high | To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections (high setting, most pessimistic). |
| Performance_NetDelay_low |
To compensate for optimistic delay estimation, add extra delay cost to long distance and high fanout connections low setting, least pessimistic). |
| Performance_Retiming | Combines retiming in
phys_opt_design with extra placement optimization and
higher router delay cost. |
| Performance_ExtraTimingOpt | Runs additional timing-driven optimizations to potentially improve overall timing slack. |
| Performance_RefinePlacement | Increase placer effort in the post-placement optimization phase, and disable timing relaxation in the router. |
| Performance_SpreadSLL | A placement variation for SSI devices with tendency to spread SLR crossings horizontally. |
| Performance_BalanceSLL | A placement variation for SSI devices with more frequent crossings of SLR boundaries. |
| Congestion_SpreadLogic_high | Spread logic throughout the device to avoid creating congested regions (high setting is the highest degree of spreading). |
| Congestion_SpreadLogic_medium | Spread logic throughout the device to avoid creating congested regions (medium setting is the medium degree of spreading). |
| Congestion_SpreadLogic_low | Spread logic throughout the device to avoid creating congested regions (low setting is the lowest degree of spreading). |
| Congestion_SpreadLogic_Explore | Similar to Congestion_SpreadLogic_high, but uses the Explore directive for routing. |
| Congestion_SSI_SpreadLogic_high | Spread logic throughout the device to avoid creating congested regions, intended for SSI devices (high setting is the highest degree of spreading). |
| Congestion_SSI_SpreadLogic_low | Spread logic throughout the device to avoid creating congested regions, intended for SSI devices (low setting is the lowest degree of spreading). |
| Area_Explore | Uses multiple optimization algorithms to get potentially fewer LUTs. |
| Area_ExploreSequential | Similar to Area_Explore but adds optimization across sequential cells. |
| Area_ExploreWithRemap | Similar to Area_Explore but adds the remap optimization to compress logic levels. |
| Power_DefaultOpt | Adds power optimization (power_opt_design) to reduce power consumption. |
| Power_ExploreArea | Combines sequential area optimization with power
optimization (power_opt_design) to
reduce power consumption. |
| Flow_RunPhysOpt | Similar to the Implementation Run Defaults, but
enables the physical optimization step (phys_opt_design). |
| Flow_RunPostRoutePhysOpt | Similar to Flow_RunPhysOpt, but enables the
Post-Route physical optimization step with the -directive Explore option. |
| Flow_RuntimeOptimized | Each implementation step trades design
performance for better run time. Physical optimization (phys_opt_design) is disabled. |
| Flow_Quick | Fastest possible runtime, all timing-driven behavior disabled. Useful for utilization estimation. |