After all logic locations have been assigned, Post-Placement Optimization
performs the final steps to improve timing and congestion. These include improving
critical path placement, BUFG Replication, and the optional BUFG insertion phase. In
the BUFG Replication phase, BUFG driven nets that span multiple SLRs will receive
their own BUFG driver for each SLR for non-Versal devices. For Versal devices, the replication is done per VNOC base and per SLR
replication is done before clock region placement. The optimization is skipped in
case of placement or routing conflicts, constraints that would prevent replication,
or timing degradation. In the BUFG insertion phase, the placer can route high fanout
nets on global routing tracks to free up fabric routing resources. High-fanout nets
(fanout > 1,000 for UltraScale and UltraScale+ and fanout > 10,000 for Versal) driving control
signals with a slack greater than 1.0 ns are considered for this optimization. The
loads are split between critical loads and high positive slack loads. The high
positive slack loads are driven through a BUFGCE which is placed at the nearest
available site to the original driver, whereas the critical loads remain connected
to the original driver. This optimization is performed only if there is no timing
degradation. The optimization is also skipped if netlist editing required by the
optimization fails. BUFG Insertion is on by default and can be disabled with the
-no_bufg_opt
option.
report_timing_summary
after placement to check the
critical paths. Paths with very large negative setup slack might need logic
restructuring, physical optimization, or floorplanning to achieve timing
closure.