BUFG Optimization - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

Mandatory logic optimization (MLO), which occurs at the beginning of link_design, supports the use of the CLOCK_BUFFER_TYPE property to insert global clock buffers. Supported values are BUFG for 7 series, and BUFG and BUFGCE for UltraScale, AMD UltraScale+™ , and Versal devices. The value NONE can be used for all architectures to suppress global clock buffer insertion through MLO and opt_design. For BUFG and BUFGCE, MLO inserts the corresponding buffer type to drive the specified net.

Use of CLOCK_BUFFER_TYPE provides the advantage of controlling buffer insertion using XDC constraints so that no design source or netlist modifications are required. Buffers inserted using CLOCK_BUFFER_TYPE are not subject to any limits, so the property must be used cautiously to avoid introducing too many global clocks into the design, which may result in placement failures. For more information, see the Vivado Design Suite Properties Reference Guide (UG912).