Power Constraints Definition - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

Power constraints define the settings needed for accurate power analysis. These settings include:

  • Operating conditions such as voltage settings, power and current budgets, and operating environment details.
  • Switching activity rates for:
    • Design objects: individual nets and pins.
    • Design object types such as block RAMs, DSPs, and transceivers.
    • Global set and reset signals.

Vivado power analysis uses timing constraints to determine switching rates and applies vectorless propagation to determine toggle rates throughout the design. Without power constraints, a default 12.5% toggle rate is used. However, applying accurate switching activity to override defaults is essential for accurate power calculations.

For further information see the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).