Timing Constraints Definition - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

Timing constraints define the frequency requirements for the design, and are written in Xilinx Design Constraints (XDC), which is based on industry standard SDC.

Without timing constraints, the Vivado Design Suite optimizes the design solely for wire length and routing congestion, and makes no effort to assess or improve design performance.