Impact of Poor Timing Constraints - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

Post-routing timing violations are sometimes the result of incorrect timing constraints.

Before you experiment with router settings, make sure that you have validated the constraints and the timing picture seen by the router. Validate timing and constraints by reviewing timing reports from the placed design before routing.

Common examples of the impact of poor timing constraints include:

  • Cross-clock paths and multi-cycle paths in which a positive hold time requirement causes route delay insertion
  • Congested areas, which can be addressed by targeted fanout optimization in RTL synthesis or through physical optimization