BUFG_FABRIC Replication for HFNs - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

For Versal designs, there is a dedicated buffer to utilize the clock tree network for non-clock pins called BUFG_FABRIC. BUFG_FABRIC are inserted to drive high fanout nets (HFN) driving more than 25,000 logical loads. For Versal SSI designs, if loads of a BUFG_FABRIC global buffer span multiple SLRs, the BUFG_FABRIC is replicated in each SLR so that each replica only drives loads within a single SLR. This reduces the overall high-fanout net (HFN) delay. This replication occurs before clock placement to ensure that each BUFG_FABRIC resource is counted against the available global clock buffer resources, thereby avoiding global clock buffer overutilization in placement.