DSP Register Opt - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

This option is used to perform various optimizations on DSP slice pipeline, input and output registers to improve timing within and to and from the DSP slices. The table below lists the available optimization.

Note: Not applicable to Versal.
Table 1. DSP Register Opt Available Optimizations
Optimization Type Configuration Required to Trigger Post Optimization State Timing Requirement
MREG to PREG MREG=1, PREG=0 MREG=0, PREG=1 Timing from MREG is critical (slack less than 0.5 ns), and timing to MREG is not critical (slack greater than 1 ns)
PREG to MREG MREG=0, PREG=1 MREG=1, PREG=0 Timing to PREG is critical (slack less than 0.5 ns), and timing from PREG is not critical (slack greater than 1 ns).
MREG to ADREG ADREG=0, MREG=1 ADREG=1, MREG=0 Timing to MREG is critical (slack less than 0.5 ns), and timing from MREG is not critical (slack greater than 1 ns)
ADREG to MREG ADREG=1, MREG=0 ADREG=0, MREG=1 Timing from ADREG is critical (slack less than 0.5 ns), and timing to ADREG is not critical (slack greater than 1 ns)
AREG/BREG push out to fabric AREG=1/2, BREG=1/2

AREG=0/1, BREG=0/1,

FDRE in fabric

Timing to AREG/BREG is critical (slack less than 0.5 ns), and timing from AREG/BREG is not critical (slack greater than 1 ns)
AREG/BREG pull in from fabric

AREG=0/1, BREG=0/1,

FDRE in fabric

AREG=1/2, BREG=1/2 Timing to DSP input is critical (slack less than 0.5 ns)

AREG and BREG to MREG

AREG=1/2, BREG=1/2, MREG=0 AREG=0/1, BREG=0/1, MREG=1 Timing from AREG/BREG is critical (slack less than 0.5 ns), and timing to AREG/BREG is not critical (slack greater than 1 ns)

MREG to AREG

and BREG

AREG=0, BREG=0, MREG=1 AREG=1, BREG=1, MREG=0 Timing to MREG is critical (slack less than 0.5 ns), and timing from MREG is not critical (slack greater than 1 ns)
PREG push out to fabric PREG=1 PREG=0, FDRE in fabric Timing from PREG is critical (slack less than 0.5 ns), and timing to PREG is not critical (slack greater than 1 ns)
PREG pull in from fabric PREG=0, FDRE in fabric PREG=1 Timing from DSP output is critical (slack less than 0.5 ns)