Shift Register Optimization - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

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2024.1 English

The shift register optimization improves timing on negative slack paths between shift register cells (SRLs) and other logic cells.

If there are timing violations to or from shift register cells (SRL16E or SRLC32E), the optimization extracts a register from the beginning or end of the SRL register chain and places it into the logic fabric to improve timing. The optimization shortens the wirelength of the original critical path.

The optimization only moves registers from a shift register to logic fabric, but never from logic fabric into a shift register, because the latter never improves timing.

The prerequisites for this optimization to occur are:

  • The SRL address must be one or greater, such that there are register stages that can be moved out of the SRL.
  • The SRL address must be a constant value, driven by logic 1 or logic 0.
  • There must be a timing violation ending or beginning from the SRL cell that is among the worst critical paths.

Certain circuit topologies are not optimized:

  • SRLC32E that are chained together to form larger shift registers are not optimized.
  • SRLC32E using a Q31 output pin.
  • SRL16E that are combined into a single LUT with both O5 and O6 output pins used.

Registers moved from SRLs to logic fabric are FDRE cells. The FDRE and SRL INIT properties are adjusted accordingly as is the SRL address. Following is an example.

A critical path begins at a shift register (SRL16E) srl_inste, as shown in the following figure.

Figure 1. Critical Path Starting at Shift Register srl_inste

After shift register optimization, the final stage of the shift register is pulled from the SRL16E and placed in the logic fabric to improve timing, as shown in the following figure.

Figure 2. Critical Path after Shift Register Optimization

The srl_inste SRL16E address is decremented to reflect one fewer internal register stage. The original critical path is now shorter as the srlopt register is placed closer to the downstream cells and the FDRE cell has a relatively faster clock-to-output delay.

Consider the following logical path, SRL + FFs + SRL, where registers between SRLs have AUTOPIPELINE attributes set.

Figure 3. Auto-pipeline path before Shift Register Optimization

Although FFs have the AUTOPIPLINE attribute, they are combined into SRL/s after shift register optimization.

As a result, the above circuit is converted into the following SRL cell.

Figure 4. Auto-pipeline path after Shift Register Optimization