Intelligent Clock Gating - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
Release Date
2024.1 English
Figure 1. Intelligent Clock Gating

Intelligent clock gating also reduces power for dedicated block RAMs in either simple dual-port or true dual-port mode, as shown in the following figure.

These blocks include several enables:

  • Array enable
  • Write enable
  • Output register clock enable

Most of the power savings comes from using the array enable. The Vivado power optimizer implements functionality to reduce power when no data is being written and when the output is not being used.

Figure 2. Leveraging Block RAM Enables