opt_design - 2024.1 English

Vivado Design Suite User Guide: Implementation (UG904)

Document ID
UG904
Release Date
2024-06-05
Version
2024.1 English

The opt_design command runs Logic Optimization.

opt_design Syntax

opt_design	[-retarget] [-propconst] [-sweep] [-bram_power_opt] [-remap] 
		[-aggressive_remap] [-resynth_remap] [-resynth_area] [-resynth_seq_area]
		[-directive <arg>] [-muxf_remap] [-hier_fanout_limit <arg>]
		[-bufg_opt] [-mbufg_opt] [-shift_register_opt] [-dsp_register_opt] 
		[-srl_remap_modes <arg>] [-control_set_merge] [‑control_set_opt] 
		[-merge_equivalent_drivers] [-carry_remap] [-debug_log] 
		[-property_opt_only] [-quiet] [-verbose]

opt_design Example Script

# Run logic optimization with the remap optimization enabled, save results in a checkpoint, report timing estimates
opt_design -directive ExploreArea 
write_checkpoint -force $outputDir/post_opt
report_timing_summary -file $outputDir/post_opt_timing_summary.rpt

The opt_design example script performs logic optimization on the in-memory design, rewriting it in the process. It also writes a design checkpoint after completing optimization, and generates a timing summary report and writes the report to the specified file.

Restrict Optimization to Listed Types

Use command line options to restrict optimization to one or more of the listed types. For example, the following is another method for skipping the block RAM optimization that is run by default:

opt_design -retarget -propconst -sweep -bufg_opt -shift_register_opt