xelab, xvhdl, and xvlog xsim Command Options

The following table lists the command options for the xelab, xvhdl, and xvlog xsim commands.

Table 1. xelab, xvhd, and xvlog Command Options
Command Option	Description	Used by Command
`-d [define] <name>[=<val>]`	Define Verilog macros. Use `-d\|--define` for each Verilog macro. The format of the macro is `<name>[=<val>]`, where `<name>` is name of the macro and `<value>` is an optional value of the macro.	xelab Parsing Design Files, xvhdl and xvlog
`-debug <kind>`	Compile with specified debugging ability turned on. The `<kind>` options are: `typical`: Most commonly used abilities, including: `line` and `wave`. `line`: HDL breakpoint. `wave`: Waveform generation, conditional execution, force value. `xlibs`: Visibility into AMD precompiled libraries. This option is only available on the command line. `off`: Turn off all debugging abilities (Default). `all`: Uses all the debug options.	xelab
`-encryptdumps`	Encrypt parsed dump of design units being compiled.	Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-f [-file] <filename>`	Read additional options from the specified file.	xelab xsim Executable Options Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-generic_top <value>`	Override generic or parameter of a top-level design unit with specified value. For example, `-generic_top "P1=10"`	xelab
`-h [-help]`	Print this help message.	xelab xsim Executable Options Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-i [include] <directory_name>`	Specify directories to be searched for files included using Verilog `include. Use `-i\|--include` for each specified search directory.	xelab Parsing Design Files, xvhdl and xvlog
`-initfile <init_filename>`	User-defined simulator initialization file to add to or override settings provided by the default xsim.ini file.	xelab Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-L [-lib] <library_name> [=<library_dir>]`	Specify search libraries for the instantiated non-VHDL design units. For example, a Verilog design unit. Use `-L\|--lib` for each search library. The format of the argument is `<name>[=<dir>]`, where `<name>` is the logical name of the library and `<library_dir>` is an optional physical directory of the library.	xelab Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-log <filename>`	Specify the log file name. Default: <xvlog\|xvhdl\|xelab\|xsim>.log.	xelab xsim Executable Options Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-maxarraysize <arg>`	Set maximum vhdl array size to be 2n (Default: n = 28, which is 228).	xelab
`-maxdelay`	Compile Verilog design units with maximum delays.	xelab
`-maxdesigndepth <arg>`	Override maximum design hierarchy depth allowed by the elaborator (Default: 5000).	xelab
`-maxlogsize <arg>`	Set the maximum size a log file can reach in MB. The default setting is unlimited.	xsim Executable Options
`-mindelay`	Compile Verilog design units with minimum delays.	xelab
`-mt <arg>`	Specifies the number of sub-compilation jobs which can be run in parallel. Possible values are `auto`, `off`, or an `integer` greater than 1. If `auto` is specified, `xelab` selects the number of parallel jobs based on the number of CPUs on the host machine. (Default = `auto`.) Advanced usage: to further control the `-mt` option, you can set the Tcl property as follows: `set_property XELAB.MT_LEVEL off\|N [get_filesets sim_1]`	xelab
`-nolog`	Suppress log file generation.	xelab xsim Executable Syntax Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-noieeewarnings`	Disable warnings from VHDL IEEE functions.	xelab
`-noname_unnamed_generate`	Do not generate name for an unnamed generate block.	xelab Parsing Design Files, xvhdl and xvlog
`-notimingchecks`	Ignore timing check constructs in Verilog specify block(s).	xelab
`-nosdfinterconnectdelays`	Ignore SDF port and interconnect delay constructs in SDF.	xelab
`-nospecify`	Ignore Verilog path delays and timing checks.	xelab
`-O <arg>`	Enable or disable optimizations. `-O 0` = Disable optimizations `-O 1` = Enable basic optimizations `-O 2` = Enable most commonly desired optimizations (Default) `-O 3` = Enable advanced optimizations Note: A lower value speeds compilation at expense of slower simulation: a higher value slows compilation but simulation runs faster.	xelab
`-override_timeunit`	Override timeunit for all Verilog modules, with the specified time unit in `-timescale` option.	xelab
`-override_timeprecision`	Override time precision for all Verilog modules, with the specified time precision in `-timescale` option.	xelab
`-pulse_e <arg>`	Path pulse error limit as percentage of path delay. Allowed values are 0 to 100 (Default is 100).	xelab
`-pulse_r <arg>`	Path pulse reject limit as percentage of path delay. Allowed values are 0 to 100 (Default is 100).	xelab
`-pulse_int_e arg`	Interconnect pulse reject limit as percentage of delay. Allowed values are 0 to 100 (Default is 100).	xelab
`-pulse_int_r <arg>`	Interconnect pulse reject limit as percentage of delay. Allowed values are 0 to 100 (Default is 100).	xelab
`-pulse_e_style <arg>`	Specify when error about pulse being shorter than module path delay should be handled. Choices are: `ondetect`: Report error right when violation is detected. `onevent`: Report error after the module path delay. Default: `onevent`	xelab
`-prj <filename>`	Specify the Vivado simulator project file containing one or more entries of `vhdl\|verilog <work lib> <HDL file name>`.	xelab Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-r [-run]`	Run the generated executable snapshot in command-line interactive mode.	xelab
`-rangecheck`	Enable runtime value range check for VHDL.	xelab
`-R [-runall]`	Run the generated executable snapshot until the end of simulation.	xelab xsim Executable Syntax
`-relax`	Relax strict language rules.	xelab Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-s [-snapshot] <arg>`	Specify the name of output simulation snapshot. Default is `<worklib>.<unit>`; for example: `work.top`. Additional unit names are concatenated using `#`; for example: `work.t1#work.t2`.	xelab
`-sdfnowarn`	Do not emit SDF warnings.	xelab
`-sdfnoerror`	Treat errors found in SDF file as warning.	xelab
`-sdfmin <arg>`	`<root>=<file>` SDF annotate `<file>` at `<root>` with minimum delay.	xelab
`-sdftyp <arg>`	`<root>=<file>` SDF annotate `<file>` at `<root>` with typical delay.	xelab
`-sdfmax <arg>`	`<root>=<file>` SDF annotate `<file>` at `<root>` with maximum delay.	xelab
`-sdfroot <root_path>`	Default design hierarchy at which SDF annotation is applied.	xelab
`-sourcelibdir <sourcelib_dirname>`	Directory for Verilog source files of uncompiled modules. Use `-sourcelibdir <sourcelib_dirname>` for each source directory.	xelab Parsing Design Files, xvhdl and xvlog
`-sourcelibext <file_extension>`	File extension for Verilog source files of uncompiled modules. Use `-sourcelibext <file extension>` for source file extension.	xelab Parsing Design Files, xvhdl and xvlog
`-sourcelibfile <filename>`	File name of a Verilog source file with uncompiled modules.	xelab Parsing Design Files, xvhdl and xvlog
`-stat`	Print tool CPU and memory usages, and design statistics.	xelab
`-sv`	Compile input files in SystemVerilog mode.	Parsing Design Files, xvhdl and xvlog
`-timescale`	Specify default timescale for Verilog modules. Default: `1ns/1ps`.	xelab
`-timeprecision_vhdl <arg>`	Specify time precision for vhdl designs. Default: `1ps`.	xelab
`-transport_int_delays`	Use transport model for interconnect delays.	xelab
`-typdelay`	Compile Verilog design units with typical delays (Default).	xelab
`-v [verbose] [0\|1\|2]`	Specify verbosity level for printing messages. Default = 0.	xelab Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-version`	Print the compiler version to screen.	xelab xsim Executable Options Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-work <library_name> [=<library_dir>]`	Specify the work library. The format of the argument is `<name>[=<dir>]` where: `<name>` is the logical name of the library. `<library_dir>` is an optional physical directory of the library.	Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog
`-sv_root <arg>`	Root directory of which DPI libraries are to be found. Default: `<current_directory/xsim.dir/xsc>`	xelab
`--sc_lib arg`	Shared library name for SystemC functions; (.dll/.so) without the file extension	xelab
`--sc_root <arg>`	Root directory of which SystemC libraries are to be found. Default: `<current_directory>/xsim.dir/work/xsc`	xelab
`-sv_lib <arg>`	Shared library name for DPI imported functions (.dll/.so) without the file extension.	xelab
`-sv_liblist <arg>`	Bootstrap file pointing to DPI shared libraries.	xelab
`-dpiheader <arg>`	Header filename for the exported and imported functions.	xelab
`-driver_display_limit <arg>`	Enable driver debugging for signals with maximum size (Default: n = 65536).	xelab
`-dpi_absolute`	Use absolute paths instead of `LD_LIBRARY_PATH` on Linux for DPI libraries that are formatted as lib<libname>.so.	xelab
`-incr`	Enable incremental analysis/elaboration in simulation.	Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog xelab
`-93_mode`	Compile VHDL in pure 93 mode.	Parsing Design Files, xvhdl and xvlog xelab
`-2008`	Compile VHDL file in 2008 mode.	Parsing Design Files, xvhdl and xvlog
`-nosignalhandlers`	Do not allow compiler to trap Antivirus, firewall signal.	Parsing Design Files, xvhdl and xvlog Parsing Design Files, xvhdl and xvlog xelab
`-dpi_stacksize <arg>`	User defined stack size for DPI task.	xelab
`-transform_timing_checkers`	Transform timing checker to Verilog process.	xelab
`-a`	Generate a standalone non-interactive simulation executable that performs run-all. Always use with `-R`. To run the simulation faster without any debug capability, use `-standalone` with `-R`. It invokes the Simulation standalone without invoking Vivado IDE. This option saves the license loading time.	xelab
`-ignore_assertions`	Ignore SystemVerilog concurrent assertions.	xelab
`-ignore_coverage`	Ignore SystemVerilog functional coverage.	xelab
`-cov_db_dir <arg>`	Functional coverage database dump directory. The coverage data is present under <arg>/xsim.covdb/<cov_db_name> directory. Default is ./.	xelab
`-cov_db_name <arg>`	Functional coverage database name. The coverage data is present under <cov_db_dir>/xsim.covdb/<arg> directory. Default is a snapshot name.	xelab
`-uvm_version <arg>`	Specify UVM version (default 1.2).	Parsing Design Files, xvhdl and xvlog xelab
`-report_assertion_pass`	Report SystemVerilog Concurrent Assertions Pass, even if there is no pass action block.	xelab
`-dup_entity_as_module`	Enable support for hierarchical references inside the Verilog hierarchy in mixed language designs. CAUTION: This might cause significant slow down of compilation.	xelab
`-cc_celldefines`	Specify if code coverage information needs to be captured for libs/modules with cell define attribute set. OFF by default.	xelab
`-cc_libs`	Specify if code coverage information needs to be captured for all the libraries specified. OFF by default.	xelab
`-cc_type arg`	Specify options for generating Code Coverage Statistics -sbct. (s)Statement Coverage, (b)Branch Coverage, (c)Condition Coverage and (t) Toggle Coverage are supported.	xelab
`-ignore_localparam_override`	Ignore localparam override	xelab

xelab, xvhdl, and xvlog xsim Command Options - 2024.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)